公开(公告)号：US09130163B2

公开(公告)日：2015-09-08

申请号：US14051212

申请日：2013-10-10

Applicant: Micron Technology, Inc

Inventor： Sanh D. Tang

IPC: H01L45/00 ,  H01L27/24 ,  G11C13/00

CPC classification number: H01L45/1253 ,  G11C13/0004 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1675 ,  H01L45/1683

Abstract: A method of forming a phase change material memory cell includes forming a number of memory structure regions, wherein the memory structure regions include a bottom electrode material and a sacrificial material, forming a number of insulator regions between the number of memory structure regions, forming a number of openings between the number of insulator regions and forming a contoured surface on the number of insulator regions by removing the sacrificial material and a portion of the number of insulator regions, forming a number of dielectric spacers on the number of insulator regions, forming a contoured opening between the number of insulator regions and exposing the bottom electrode material by removing a portion of the number of dielectric spacers, and forming a phase change material in the opening between the number of insulator regions.

Abstract translation: 形成相变材料存储单元的方法包括形成多个存储结构区域，其中存储结构区域包括底电极材料和牺牲材料，在存储结构区域的数量之间形成多个绝缘体区域，形成 多个绝缘体区域之间的开口数，并且通过去除牺牲材料和绝缘体区域的数量的一部分在绝缘体区域的数量上形成绝缘体区域的轮廓表面，在绝缘体区域的数量上形成多个电介质间隔物，形成绝缘体区域 在多个绝缘体区域之间形成轮廓的开口，并通过去除一部分介电间隔物而露出底部电极材料，并且在绝缘体区域之间的开口中形成相变材料。

公开(公告)号：US09123888B2

公开(公告)日：2015-09-01

申请号：US14448352

申请日：2014-07-31

Applicant: Micron Technology, Inc.

Inventor： Scott E. Sills ,  Gurtej S. Sandhu ,  Sanh D. Tang ,  John Smythe

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1226 ,  H01L27/2409 ,  H01L27/2427 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/085 ,  H01L45/124 ,  H01L45/1266 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/145 ,  H01L45/146 ,  H01L45/148

Abstract: Some embodiments include memory cells. The memory cells may have a first electrode, and a trench-shaped programmable material structure over the first electrode. The trench-shape defines an opening. The programmable material may be configured to reversibly retain a conductive bridge. The memory cell may have an ion source material directly against the programmable material, and may have a second electrode within the opening defined by the trench-shaped programmable material. Some embodiments include arrays of memory cells. The arrays may have first electrically conductive lines, and trench-shaped programmable material structures over the first lines. The trench-shaped structures may define openings within them. Ion source material may be directly against the programmable material, and second electrically conductive lines may be over the ion source material and within the openings defined by the trench-shaped structures.

Abstract translation: 一些实施例包括存储器单元。 存储单元可以具有第一电极和在第一电极上方的沟槽状可编程材料结构。 沟槽形状限定开口。 可编程材料可以被配置为可逆地保持导电桥。 存储单元可以具有直接抵靠可编程材料的离子源材料，并且可以在由沟槽状可编程材料限定的开口内具有第二电极。 一些实施例包括存储器单元阵列。 阵列可以具有第一导电线，以及在第一线上的沟槽状可编程材料结构。 沟槽状结构可以在其内限定开口。 离子源材料可以直接抵靠可编程材料，并且第二导电线可以在离子源材料之上并且在由沟槽状结构限定的开口内。

公开(公告)号：US20150221864A1

公开(公告)日：2015-08-06

申请号：US14687738

申请日：2015-04-15

Applicant: Micron Technology, Inc.

Inventor： Scott E. Sills ,  Gurtej S. Sandhu ,  Sanh D. Tang ,  John Smythe

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1226 ,  H01L27/2409 ,  H01L27/2427 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/085 ,  H01L45/124 ,  H01L45/1266 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/145 ,  H01L45/146 ,  H01L45/148

Abstract: Some embodiments include memory cells. The memory cells may have a first electrode, and a trench-shaped programmable material structure over the first electrode. The trench-shape defines an opening. The programmable material may be configured to reversibly retain a conductive bridge. The memory cell may have an ion source material directly against the programmable material, and may have a second electrode within the opening defined by the trench-shaped programmable material. Some embodiments include arrays of memory cells. The arrays may have first electrically conductive lines, and trench-shaped programmable material structures over the first lines. The trench-shaped structures may define openings within them. Ion source material may be directly against the programmable material, and second electrically conductive lines may be over the ion source material and within the openings defined by the trench-shaped structures.

Abstract translation: 一些实施例包括存储器单元。 存储单元可以具有第一电极和在第一电极上方的沟槽状可编程材料结构。 沟槽形状限定开口。 可编程材料可以被配置为可逆地保持导电桥。 存储单元可以具有直接抵靠可编程材料的离子源材料，并且可以在由沟槽状可编程材料限定的开口内具有第二电极。 一些实施例包括存储器单元阵列。 阵列可以具有第一导电线，以及在第一线上的沟槽状可编程材料结构。 沟槽状结构可以在其内限定开口。 离子源材料可以直接抵靠可编程材料，并且第二导电线可以在离子源材料之上并且在由沟槽状结构限定的开口内。

公开(公告)号：US20150137214A1

公开(公告)日：2015-05-21

申请号：US14606415

申请日：2015-01-27

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  David H. Wells ,  Tuman E. Allen

IPC: H01L29/792 ,  H01L21/762 ,  H01L29/16 ,  H01L21/28 ,  H01L29/06 ,  H01L29/51 ,  H01L21/02 ,  H01L29/66 ,  H01L29/161

CPC classification number: H01L29/792 ,  H01L21/02532 ,  H01L21/28282 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/84 ,  H01L27/1021 ,  H01L27/1027 ,  H01L27/10802 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/16 ,  H01L29/161 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881

Abstract: Semiconductor structures that include bodies of a semiconductor material spaced apart from an underlying substrate. The bodies may be physically separated from the substrate by at least one of a dielectric material, an open volume and a conductive material. The bodies may be electrically coupled by one or more conductive structures, which may be used as an interconnect structure to electrically couple components of memory devices. By providing isolation between the bodies, the semiconductor structure provides the properties of a conventional SOI substrate (e.g., high speed, low power, increased device density and isolation) while substantially reducing fabrication acts and costs associated with such SOI substrates. Additionally, the semiconductor structures of the present disclosure provide reduced parasitic coupling and current leakage due to the isolation of the bodies by the intervening dielectric material.

Abstract translation: 半导体结构包括与下面的衬底间隔开的半导体材料的主体。 物体可以通过介电材料，开放体积和导电材料中的至少一种与基底物理分离。 主体可以通过一个或多个导电结构电耦合，其可以用作互连结构以电耦合存储器件的部件。 通过在主体之间提供隔离，半导体结构提供常规SOI衬底（例如，高速度，低功率，增加的器件密度和隔离）的性质，同时显着减少与这种SOI衬底相关联的制造动作和成本。 另外，本公开的半导体结构由于通过中间介电材料隔离物体而提供减小的寄生耦合和电流泄漏。

公开(公告)号：US08980699B2

公开(公告)日：2015-03-17

申请号：US13965463

申请日：2013-08-13

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang

IPC: H01L21/332 ,  H01L29/66 ,  H01L27/102 ,  H01L29/749 ,  H01L29/40

CPC classification number: H01L27/1027 ,  H01L21/28088 ,  H01L21/32051 ,  H01L21/32055 ,  H01L21/32133 ,  H01L29/401 ,  H01L29/42308 ,  H01L29/66363 ,  H01L29/749

Abstract: Semiconductor devices including a plurality of thyristor-based memory cells, each having a cell size of 4F2, and methods for forming the same are provided. The thyristor-based memory cells each include a thyristor having vertically superposed regions of alternating dopant types, and a control gate. The control gate may be electrically coupled with one or more of the thyristors and may be operably coupled to a voltage source. The thyristor-based memory cells may be formed in an array on a conductive strap, which may function as a cathode or a data line. A system may be formed by integrating the semiconductor devices with one or more memory access devices or conventional logic devices, such as a complementary metal-oxide-semiconductor (CMOS) device.

Abstract translation: 提供了包括多个基于晶闸管的存储单元的半导体器件，每个存储单元的单元尺寸为4F2，以及形成该晶体管的存储单元的形成方法。 基于晶闸管的存储单元各自包括具有交替掺杂剂类型的垂直叠置区域的晶闸管和控制栅极。 控制栅极可以与一个或多个晶闸管电耦合，并且可以可操作地耦合到电压源。 基于晶闸管的存储单元可以形成为阵列中的导电带，其可以用作阴极或数据线。 可以通过将半导体器件与诸如互补金属氧化物半导体（CMOS）器件的一个或多个存储器访问器件或常规逻辑器件集成来形成系统。

公开(公告)号：US08866209B2

公开(公告)日：2014-10-21

申请号：US13938973

申请日：2013-07-10

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  John K. Zahurak

IPC: H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC classification number: H01L21/762 ,  H01L21/32 ,  H01L27/0814 ,  H01L27/108 ,  H01L27/10808 ,  H01L27/2454 ,  H01L27/2472 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/861 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

Abstract: Semiconductor arrays including a plurality of access devices disposed on a buried conductive line and methods for forming the same are provided. The access devices each include a transistor having a source region and drain region spaced apart by a channel region of opposite dopant type and an access line associated with the transistor. The access line may be electrically coupled with one or more of the transistors and may be operably coupled to a voltage source. The access devices may be formed in an array on one or more conductive lines. A system may be formed by integrating the semiconductor devices with one or more memory semiconductor arrays or conventional logic devices, such as a complementary metal-oxide-semiconductor (CMOS) device.

Abstract translation: 提供了包括设置在埋地导线上的多个访问装置的半导体阵列及其形成方法。 接入装置各自包括具有由相反掺杂剂类型的沟道区域隔开的源极区域和漏极区域以及与该晶体管相关联的存取管线的晶体管。 接入线路可以与一个或多个晶体管电耦合，并且可以可操作地耦合到电压源。 访问设备可以以一个或多个导线上的阵列形成。 可以通过将半导体器件与诸如互补金属氧化物半导体（CMOS）器件的一个或多个存储器半导体阵列或常规逻辑器件集成来形成系统。

公开(公告)号：US20140269047A1

公开(公告)日：2014-09-18

申请号：US14289162

申请日：2014-05-28

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Mike N. Nguyen

IPC: H01L27/108 ,  H01L29/66

CPC classification number: H01L27/10802 ,  H01L27/1203 ,  H01L29/66833 ,  H01L29/7841

Abstract: An apparatus is disclosed for a memory cell having a floating body. A memory cell may include a transistor over an insulation layer, the transistor including a source, and a drain. The memory cell may also include a floating body including a first region positioned between the source and the drain, a second region positioned remote from each of the source and drain, and a passage extending through the insulation layer and coupling the first region to the second region. Additionally, the memory cell may include a bias gate at least partially surrounding the second region and configured for operably coupling to a bias voltage. Furthermore, the memory cell may include a plurality of dielectric layers, wherein each outer vertical surface of the second region has a dielectric layer of the plurality adjacent thereto.

Abstract translation: 公开了一种具有浮体的存储单元的装置。 存储单元可以包括绝缘层上的晶体管，晶体管包括源极和漏极。 存储单元还可以包括浮动体，其包括位于源极和漏极之间的第一区域，远离源极和漏极中的每一个定位的第二区域，以及延伸穿过绝缘层并且将第一区域耦合到第二区域的第二区域 地区。 另外，存储单元可以包括至少部分地围绕第二区域并被配置为可操作地耦合到偏置电压的偏置栅极。 此外，存储单元可以包括多个电介质层，其中第二区域的每个外部垂直表面具有与其相邻的多个电介质层。

公开(公告)号：US08822974B2

公开(公告)日：2014-09-02

申请号：US13856561

申请日：2013-04-04

Applicant: Micron Technology, Inc.

Inventor： Scott E. Sills ,  Gurtej S. Sandhu ,  Sanh D. Tang ,  John Smythe

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1226 ,  H01L27/2409 ,  H01L27/2427 ,  H01L27/2463 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/085 ,  H01L45/124 ,  H01L45/1266 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/145 ,  H01L45/146 ,  H01L45/148

Abstract: Some embodiments include memory cells. The memory cells may have a first electrode, and a trench-shaped programmable material structure over the first electrode. The trench-shape defines an opening. The programmable material may be configured to reversibly retain a conductive bridge. The memory cell may have an ion source material directly against the programmable material, and may have a second electrode within the opening defined by the trench-shaped programmable material. Some embodiments include arrays of memory cells. The arrays may have first electrically conductive lines, and trench-shaped programmable material structures over the first lines. The trench-shaped structures may define openings within them. Ion source material may be directly against the programmable material, and second electrically conductive lines may be over the ion source material and within the openings defined by the trench-shaped structures.

Abstract translation: 一些实施例包括存储器单元。 存储单元可以具有第一电极和在第一电极上方的沟槽状可编程材料结构。 沟槽形状限定开口。 可编程材料可被配置为可逆地保持导电桥。 存储单元可以具有直接抵靠可编程材料的离子源材料，并且可以在由沟槽状可编程材料限定的开口内具有第二电极。 一些实施例包括存储器单元阵列。 阵列可以具有第一导电线，以及在第一线上的沟槽状可编程材料结构。 沟槽状结构可以在其内限定开口。 离子源材料可以直接抵靠可编程材料，并且第二导电线可以在离子源材料之上并且在由沟槽状结构限定的开口内。

公开(公告)号：US08743589B2

公开(公告)日：2014-06-03

申请号：US13850348

申请日：2013-03-26

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu ,  Sanh D. Tang

IPC: G11C11/00 ,  G11C5/02 ,  G11C5/06

CPC classification number: G11C13/0002 ,  G11C5/02 ,  G11C5/025 ,  G11C5/06 ,  G11C8/12 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/004 ,  G11C2213/71 ,  H01L27/0688 ,  H01L27/101

Abstract: An array of vertically stacked tiers of non-volatile cross point memory cells includes a plurality of horizontally oriented word lines within individual tiers of memory cells. A plurality of horizontally oriented global bit lines having local vertical bit line extensions extend through multiple of the tiers. Individual of the memory cells comprise multi-resistive state material received between one of the horizontally oriented word lines and one of the local vertical bit line extensions where such cross, with such ones comprising opposing conductive electrodes of individual memory cells where such cross. A plurality of bit line select circuits individually electrically and physically connects to individual of the local vertical bit line extensions and are configured to supply a voltage potential to an individual of the global horizontal bit lines. Other embodiments and aspects are disclosed.

Abstract translation: 垂直堆叠层的非易失性交叉点存储单元的阵列包括在存储单元的各个层内的多个水平取向的字线。 具有局部垂直位线延伸的多个水平定向的全局位线延伸穿过多个层。 存储单元的个体包括在水平定向的字线之一和本地垂直位线延伸之一中的一个之间接收的多电阻状态材料，其中这些交叉具有这样的交叉的单个存储器单元的相对的导电电极。 多个位线选择电路单独地电和物理地连接到本地垂直位线延伸的个体，并且被配置为向全局水平位线的个体提供电压电位。 公开了其它实施例和方面。

公开(公告)号：US20140097399A1

公开(公告)日：2014-04-10

申请号：US14051212

申请日：2013-10-10

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang

IPC: H01L45/00

CPC classification number: H01L45/1253 ,  G11C13/0004 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1675 ,  H01L45/1683

Abstract: Methods, devices, and systems associated with phase change material memory are described herein. In one or more embodiments, a method of forming a phase change material memory cell includes forming a number of memory structure regions, wherein the memory structure regions include a bottom electrode material and a sacrificial material, forming a number of insulator regions between the number of memory structure regions, forming a number of openings between the number of insulator regions and forming a contoured surface on the number of insulator regions by removing the sacrificial material and a portion of the number of insulator regions, forming a number of dielectric spacers on the number of insulator regions, forming a contoured opening between the number of insulator regions and exposing the bottom electrode material by removing a portion of the number of dielectric spacers, and forming a phase change material in the opening between the number of insulator regions.

Abstract translation: 本文描述了与相变材料存储器相关联的方法，装置和系统。 在一个或多个实施例中，形成相变材料存储单元的方法包括形成多个存储器结构区域，其中存储器结构区域包括底部电极材料和牺牲材料，在多个绝缘体区域之间形成多个绝缘体区域 存储器结构区域，在多个绝缘体区域之间形成多个开口，并通过去除牺牲材料和绝缘体区域的数量的一部分在绝缘体区域的数量上形成轮廓表面，在数量上形成多个电介质间隔物 的绝缘体区域之间，在多个绝缘体区域之间形成轮廓的开口，并通过去除一部分电介质间隔物而露出底部电极材料，并且在绝缘体区域之间的开口中形成相变材料。