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    MEMORY APPARATUS, SYSTEMS, AND METHODS
    31.
    发明申请
    MEMORY APPARATUS, SYSTEMS, AND METHODS 有权
    内存设备，系统和方法

    公开(公告)号：US20150325309A1

    公开(公告)日：2015-11-12

    申请号：US14803918

    申请日：2015-07-20

    Applicant: Micron Technology, Inc.

    Inventor： Violante Moschiano ,  Tommaso Vali ,  Giovanni Naso ,  Vishal Sarin ,  William Henry Radke ,  Theodore T. Pekny

    IPC: G11C16/34 ,  G11C11/56

    CPC classification number: G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3427 ,  G11C2211/5641

    Abstract: Threshold voltages in a charge storage memory are controlled by threshold voltage placement, such as to provide more reliable operation and to reduce the influence of factors such as neighboring charge storage elements and parasitic coupling. Pre-compensation or post-compensation of threshold voltage for neighboring programmed aggressor memory cells reduces the threshold voltage uncertainty in a flash memory system. Using a buffer having a data structure such as a lookup table provides for programmable threshold voltage distributions that enables the distribution of data states in a multi-level cell flash memory to be tailored, such as to provide more reliable operation. Additional apparatus, systems, and methods are provided.

    Abstract translation: 电荷存储存储器中的阈值电压由阈值电压放置来控制，例如提供更可靠的操作并减少诸如相邻电荷存储元件和寄生耦合的因素的影响。 对于相邻编程的侵略存储器单元的阈值电压的预补偿或后补偿降低了闪存系统中的阈值电压不确定性。 使用具有诸如查找表之类的数据结构的缓冲器提供了可编程的阈值电压分布，使得能够定制多级单元闪存中的数据状态的分布，例如提供更可靠的操作。 提供附加的装置，系统和方法。

    Programming methods and memories
    32.
    发明授权
    Programming methods and memories 有权
    编程方法和记忆

    公开(公告)号：US09177651B2

    公开(公告)日：2015-11-03

    申请号：US14108822

    申请日：2013-12-17

    Applicant: Micron Technology, Inc.

    Inventor： Vishal Sarin ,  William H. Radke ,  Frankie F. Roohparvar

    IPC: G11C11/00 ,  G11C16/10 ,  G11C16/04 ,  G11C16/34

    CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3454

    Abstract: Methods of programming a memory and memories are disclosed. In at least one embodiment, a memory is programmed by determining a pretarget threshold voltage for a selected cell, wherein the pretarget threshold voltage is determined using pretarget threshold voltage values for at least one neighbor cell of the selected cell.

    Abstract translation: 公开了对存储器和存储器进行编程的方法。 在至少一个实施例中，通过确定所选择的单元的预定阈值电压来对存储器进行编程，其中使用所选单元的至少一个相邻单元的预定阈值电压值来确定预定阈值电压。

    APPARATUSES AND METHODS FOR LIMITING STRING CURRENT IN A MEMORY
    35.
    发明申请
    APPARATUSES AND METHODS FOR LIMITING STRING CURRENT IN A MEMORY 有权
    限制存储器中的电流的装置和方法

    公开(公告)号：US20140376313A1

    公开(公告)日：2014-12-25

    申请号：US13924310

    申请日：2013-06-21

    Applicant: Micron Technology, Inc.

    Inventor： Vishal Sarin

    IPC: G11C16/30

    CPC classification number: G11C16/30 ,  G11C7/14 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3459

    Abstract: Apparatuses, current control circuits, and methods for limiting string current in a memory are described. An example apparatus includes a memory cell string including a memory cell. The example apparatus further includes a sense circuit configured to sense a current through the memory cell string, and a select gate configured to couple the memory cell string to a source based on a select gate voltage. The example apparatus further includes a current control circuit coupled to the select gate. The current control circuit is configured to limit current through the memory cell string during a memory access operation based on a reference current.

    Abstract translation: 描述了用于限制存储器中的串电流的装置，电流控制电路和方法。 示例性装置包括包括存储单元的存储单元串。 该示例设备还包括：感测电路，被配置为感测通过存储单元串的电流;以及选择栅极，被配置为基于选择栅极电压将存储单元串耦合到源极。 该示例设备还包括耦合到选择门的电流控制电路。 电流控制电路被配置为基于参考电流在存储器访问操作期间限制通过存储器单元串的电流。

    METHOD FOR KINK COMPENSATION IN A MEMORY
    36.
    发明申请
    METHOD FOR KINK COMPENSATION IN A MEMORY 有权
    闪存补偿方法

    公开(公告)号：US20140043912A1

    公开(公告)日：2014-02-13

    申请号：US14045492

    申请日：2013-10-03

    Applicant: Micron Technology, Inc.

    Inventor： Violante Moschiano ,  Frankie Roohparvar ,  Giovanni Santin ,  Vishal Sarin ,  Allahyar Vahidimowlavi ,  Tommaso Vali

    IPC: G11C16/10

    CPC classification number: G11C16/10 ,  G11C11/404 ,  G11C11/5628 ,  G11C16/3404

    Abstract: This disclosure concerns memory kink compensation. One method embodiment includes applying a number of sequentially incrementing programming pulses to a memory cell, with the sequential programming pulses incrementing by a first programming pulse step voltage magnitude. A seeding voltage is applied after applying the number of sequentially incrementing programming pulses. A next programming pulse is applied after applying the seeding voltage, with the next programming pulse being adjusted relative to a preceding one of the sequentially incrementing programming pulses by a second programming pulse step voltage magnitude. The second programming pulse step voltage magnitude can be less than the first programming pulse step voltage magnitude.

    Abstract translation: 本公开涉及存储器扭结补偿。 一个方法实施例包括将多个顺序递增的编程脉冲施加到存储器单元，其中顺序编程脉冲通过第一编程脉冲阶跃电压幅度递增。 在施加顺序递增的编程脉冲数之后施加接种电压。 在施加播种电压之后施加下一个编程脉冲，其中下一个编程脉冲相对于先前的一个顺序递增的编程脉冲通过第二编程脉冲阶跃电压幅度被调整。 第二个编程脉冲阶跃电压幅度可以小于第一个编程脉冲阶跃电压幅度。

    MEMORY CONTROLLER SELF-CALIBRATION FOR REMOVING SYSTEMIC INFLUENCE
    37.
    发明申请
    MEMORY CONTROLLER SELF-CALIBRATION FOR REMOVING SYSTEMIC INFLUENCE 有权

    公开(公告)号：US20130135936A1

    公开(公告)日：2013-05-30

    申请号：US13749850

    申请日：2013-01-25

    Applicant: Micron Technology, Inc.

    Inventor： Frankie F. Roohparvar ,  Vishal Sarin ,  Jung-Sheng Hoei

    IPC: G11C16/10

    CPC classification number: G11C16/10 ,  G11C16/04 ,  G11C16/20 ,  G11C29/028 ,  G11C29/12005 ,  G11C29/50 ,  G11C29/50004 ,  G11C2029/5004

    Abstract: Self-calibration for a memory controller is performed by writing a voltage to a selected cell. Adjacent cells around the selected cell are programmed. After each of the adjacent programming operations, the voltage on the selected cell is read to determine any change in voltage caused by systemic offsets such as, for example, floating gate-to-floating gate coupling. These changes are averaged and stored in a table as an offset for use in adjusting a programming voltage or a read voltage in a particular area of memory represented by the offset. Self calibration method for temperature is determined by writing cells at different temperatures and reading at different temperatures to generate temperature offset tables for the write path and read path. These offset tables are used to adjust for systematic temperature related offsets during programming and during read.

    MEMORY DEVICES FOR PATTERN MATCHING
    39.
    发明申请
    MEMORY DEVICES FOR PATTERN MATCHING 有权

    公开(公告)号：US20210217475A1

    公开(公告)日：2021-07-15

    申请号：US17218243

    申请日：2021-03-31

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Luca De Santis ,  Tommaso Vali ,  Kenneth J. Eldredge ,  Vishal Sarin

    IPC: G11C15/04 ,  G11C16/10 ,  G11C16/04 ,  H01L27/00 ,  G11C13/06

    Abstract: Memory devices might include control circuitry that, when checking for a match of a stored digit of data and a received digit of data, might be configured to cause the memory device to apply a first voltage level to a control gate of a first memory cell of a memory cell pair, apply a second voltage level different than the first voltage level to a control gate of a second memory cell of that memory cell pair, determine whether that memory cell pair is deemed to be activated or deactivated in response to applying the first and second voltage levels, and deem a match between the stored digit of data and a received digit of data in response, in part, to whether that memory cell pair is deemed to be deactivated.

    Methods and apparatus for pattern matching in a memory containing sets of memory elements
    40.
    发明授权
    Methods and apparatus for pattern matching in a memory containing sets of memory elements 有权

    公开(公告)号：US10984864B2

    公开(公告)日：2021-04-20

    申请号：US16517846

    申请日：2019-07-22

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Luca De Santis ,  Tommaso Vali ,  Kenneth J. Eldredge ,  Vishal Sarin

    IPC: G11C15/04 ,  G11C16/10 ,  G11C16/04 ,  H01L27/00 ,  G11C13/06 ,  G11C29/52

    Abstract: Methods include receiving a pattern to be searched in a memory having a plurality of sets of memory elements with each set coupled to a separate data line and corresponding to a same set of bit positions of the pattern. Methods further include receiving a pattern of data to be programmed into a memory, programming a first data state into one memory cell of each cell pair of a plurality of cell pairs of a memory array, and programing a second data state into another memory cell of each cell pair of the plurality of cell pairs for each bit position of the pattern. Memory configured to facilitate such methods include a plurality of cell pairs, each cell pair of the plurality of cell pairs programmed to store a same bit of data corresponding to a particular bit position of a pattern to be searched in the memory.

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