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    BOOTING IN SYSTEMS HAVING DEVICES COUPLED IN A CHAINED CONFIGURATION
    31.
    发明申请
    BOOTING IN SYSTEMS HAVING DEVICES COUPLED IN A CHAINED CONFIGURATION 有权
    在具有连接配置中的设备的系统中进行操作

    公开(公告)号：US20140025943A1

    公开(公告)日：2014-01-23

    申请号：US14034852

    申请日：2013-09-24

    Applicant: Micron Technology, Inc.

    Inventor： William H. Radke ,  Victor Y. Tsai ,  Peter Feeley ,  Neal A. Galbo ,  Robert N. Leibowitz

    IPC: G06F9/44

    CPC classification number: G06F9/4411 ,  G06F9/4401

    Abstract: The present disclosure includes methods, devices, and systems for booting in systems having devices coupled in a chained configuration. One or more embodiments include a host and a number of devices coupled to the host in a chained configuration, wherein at least one of the number of devices is a bootable device and the at least one bootable device is not directly coupled to the host.

    Abstract translation: 本公开包括用于在具有以链接配置耦合的设备的系统中引导的方法，设备和系统。 一个或多个实施例包括以链接配置耦合到主机的主机和多个设备，其中，多个设备中的至少一个是可引导设备，并且所述至少一个可启动设备不直接耦合到主机。

    FRACTIONAL BITS IN MEMORY CELLS
    32.
    发明申请
    FRACTIONAL BITS IN MEMORY CELLS 有权
    记忆细胞中的分位

    公开(公告)号：US20140003143A1

    公开(公告)日：2014-01-02

    申请号：US14020523

    申请日：2013-09-06

    Applicant: Micron Technology, Inc.

    Inventor： William H. Radke

    IPC: G11C16/04

    CPC classification number: G11C11/5628 ,  G06F11/1008 ,  G11C11/5621 ,  G11C11/5642 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/10 ,  G11C29/00 ,  G11C2211/5641

    Abstract: Methods, devices, modules, and systems for programming memory cells can include storing charges corresponding to a data state that represents an integer number of bits in a set of memory cells. Programming memory cells can include storing a charge in a cell of the set, where the charge corresponds to a programmed state, where the programmed state represents a fractional number of bits, and where the programmed state denotes a digit of the data state as expressed by a number in base N, where N is equal to 2B, rounded up to an integer, and where B is equal to the fractional number of bits represented by the programmed state.

    Abstract translation: 用于编程存储器单元的方法，设备，模块和系统可以包括存储与在一组存储器单元中表示整数位的数据状态相对应的电荷。 编程存储器单元可以包括将电荷存储在组的单元中，其中电荷对应于编程状态，其中编程状态表示分数位数，并且其中编程状态表示数据状态的数字，如 基数N中的数，其中N等于2B，向上舍入为整数，并且其中B等于由编程状态表示的分数的位数。

    Methods, devices, and systems for dealing with threshold voltage change in memory devices
    33.
    发明授权
    Methods, devices, and systems for dealing with threshold voltage change in memory devices 有权
    用于处理存储器件中阈值电压变化的方法，器件和系统

    公开(公告)号：US08576632B2

    公开(公告)日：2013-11-05

    申请号：US13667414

    申请日：2012-11-02

    Applicant: Micron Technology, Inc.

    Inventor： Zhenlei Shen ,  William H. Radke ,  Peter Feeley

    IPC: G11C16/06

    CPC classification number: G11C16/34 ,  G11C11/5642 ,  G11C16/26 ,  G11C16/3495

    Abstract: The present disclosure includes methods, devices, and systems for dealing with threshold voltage change in memory devices. A number of embodiments include an array of memory cells and control circuitry having sense circuitry coupled to the array. The control circuitry is configured to determine changes in threshold voltages (Vts) associated with the memory cells without using a reference cell, and adjust the sense circuitry based on the determined changes and without using a reference cell.

    Abstract translation: 本公开包括用于处理存储器件中的阈值电压变化的方法，装置和系统。 多个实施例包括具有耦合到阵列的感测电路的存储器单元阵列和控制电路。 控制电路被配置为确定与存储器单元相关联的阈值电压（Vts）的变化而不使用参考单元，并且基于所确定的变化并且不使用参考单元来调整感测电路。

    ERROR RECOVERY STORAGE ALONG A MEMORY STRING
    34.
    发明申请
    ERROR RECOVERY STORAGE ALONG A MEMORY STRING 有权
    存储器字符串中的错误恢复存储

    公开(公告)号：US20130283130A1

    公开(公告)日：2013-10-24

    申请号：US13919982

    申请日：2013-06-17

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： William H. Radke

    IPC: G06F11/10

    CPC classification number: G06F11/1008 ,  G06F11/1072 ,  H03M13/256 ,  H03M13/2909

    Abstract: Apparatus and methods store error recovery data in different dimensions of a memory array. For example, in one dimension, block error correction codes (ECC) are used, and in another dimension, supplemental error correction codes, such as convolutional codes, are used. By using separate dimensions, the likelihood that a defect affects both error recovery techniques is lessened, thereby increasing the probability that error recovery can be performed successfully. In one example, block error correction codes are used for data stored along rows, and this data is stored in one level of multiple-level cells of the array. Supplemental error correction codes are used for data stored along columns, such as along the cells of a string, and the supplemental error correction codes are stored in a different level than the error correction codes.

    Abstract translation: 设备和方法存储存储器阵列的不同维度的错误恢复数据。 例如，在一个维度中，使用块纠错码（ECC），并且在另一维度中，使用补码纠错码，例如卷积码。 通过使用单独的维度，缺陷影响两种错误恢复技术的可能性减弱，从而增加了可以成功执行错误恢复的概率。 在一个示例中，块错误校正码用于沿着行存储的数据，并且该数据被存储在阵列的多级单元中。 补充纠错码用于沿列存储的数据，例如沿着字符串的单元格，并且补充纠错码存储在与纠错码不同的电平上。

    METHODS, DEVICES, AND SYSTEMS FOR DEALING WITH THRESHOLD VOLTAGE CHANGE IN MEMORY DEVICES
    35.
    发明申请
    METHODS, DEVICES, AND SYSTEMS FOR DEALING WITH THRESHOLD VOLTAGE CHANGE IN MEMORY DEVICES 有权
    用于处理存储器件中阈值电压变化的方法，器件和系统

    公开(公告)号：US20130058168A1

    公开(公告)日：2013-03-07

    申请号：US13667414

    申请日：2012-11-02

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Zhenlei Shen ,  William H. Radke ,  Peter Feeley

    IPC: G11C16/06

    CPC classification number: G11C16/34 ,  G11C11/5642 ,  G11C16/26 ,  G11C16/3495

    Abstract: The present disclosure includes methods, devices, and systems for dealing with threshold voltage change in memory devices. A number of embodiments include an array of memory cells and control circuitry having sense circuitry coupled to the array. The control circuitry is configured to determine changes in threshold voltages (Vts) associated with the memory cells without using a reference cell, and adjust the sense circuitry based on the determined changes and without using a reference cell.

    Abstract translation: 本公开包括用于处理存储器件中的阈值电压变化的方法，装置和系统。 多个实施例包括具有耦合到阵列的感测电路的存储器单元阵列和控制电路。 控制电路被配置为确定与存储器单元相关联的阈值电压（Vts）的变化而不使用参考单元，并且基于所确定的变化并且不使用参考单元来调整感测电路。

    Memory devices having differently configured blocks of memory cells
    37.
    发明授权
    Memory devices having differently configured blocks of memory cells 有权

    公开(公告)号：US10409673B2

    公开(公告)日：2019-09-10

    申请号：US15414699

    申请日：2017-01-25

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： William H. Radke ,  Tommaso Vali ,  Michele Incarnati

    IPC: G11C29/00 ,  G06F11/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G06F3/06 ,  G06F12/02 ,  G06F12/06 ,  G11C29/52

    Abstract: A memory device has a plurality of individually erasable blocks of memory cells and a controller configured to configure a first block of the plurality of blocks of memory cells in a first configuration comprising one or more groups of overhead data memory cells, to configure a second block of the plurality of blocks of memory cells in a second configuration comprising a group of user data memory cells and a group of overhead data memory cells, and to configure a third block of the plurality of blocks of memory cells in a third configuration comprising only a group of user data memory cells. The group of overhead data memory cells of the second block of memory cells has a different storage capacity than at least one group of overhead data memory cells of the one or more groups of overhead data memory cells of the first block.

    Data conditioning to improve flash memory reliability
    40.
    发明授权
    Data conditioning to improve flash memory reliability 有权
    数据调理提高闪存的可靠性

    公开(公告)号：US09471425B2

    公开(公告)日：2016-10-18

    申请号：US14308040

    申请日：2014-06-18

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： William H. Radke ,  Vishal Sarin ,  Jung-Sheng Hoei

    IPC: G06F12/02 ,  G06F11/10 ,  G11C11/56 ,  G11C29/52

    CPC classification number: G06F11/1072 ,  G06F12/0246 ,  G06F2212/7205 ,  G06F2212/7208 ,  G11C11/5628 ,  G11C29/52 ,  G11C2211/5641

    Abstract: Methods for managing data stored in a memory device facilitate managing utilization of memory of different densities. The methods include reading first data from a first number of pages or blocks of memory cells having a first density, performing a data handling operation on the read first data to generate second data, and writing the second data to a second number of pages or blocks of memory cells having a second density, wherein the second density is different than the first density, and wherein the second number is different than the first number.

    Abstract translation: 用于管理存储在存储设备中的数据的方法便于管理不同密度的存储器的利用。 所述方法包括从具有第一密度的第一页数或块的存储单元读取第一数据，对读取的第一数据执行数据处理操作以产生第二数据，以及将第二数据写入第二数量的页或块 的具有第二密度的存储单元，其中所述第二密度不同于所述第一密度，并且其中所述第二数量不同于所述第一密度。

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