公开(公告)号：US06524914B1

公开(公告)日：2003-02-25

申请号：US09699972

申请日：2000-10-30

申请人： Yue-song He ,  Sameer Haddad ,  Timothy Thurgate ,  Chi Chang

发明人： Yue-song He ,  Sameer Haddad ,  Timothy Thurgate ,  Chi Chang

IPC分类号： H01L218247

CPC分类号： H01L29/66825 ,  H01L29/66833

摘要： One aspect of the present invention relates to a method of making a flash memory cell involving the steps of providing a substrate having a flash memory cell thereon; forming a self-aligned source mask over the substrate, the self aligned source mask having openings corresponding to source lines; implanting a source dopant of a first type in the substrate through the openings in the self-aligned source mask corresponding to source lines; removing the self-aligned source mask from the substrate; cleaning the substrate; and implanting a medium dosage drain implant of a second type to form a source region and a drain region in the substrate adjacent the flash memory cell.

摘要翻译： 本发明的一个方面涉及一种制造闪存单元的方法，所述闪存单元包括以下步骤：提供其上具有闪存单元的基板; 在衬底上形成自对准源掩模，所述自对准源掩模具有对应于源极线的开口; 通过对应于源极线的自对准源掩模中的开口将衬底中的第一类型源掺杂剂注入到衬底中; 从衬底去除自对准源掩模; 清洗基材; 以及植入第二类型的介质剂量漏极注入以在所述衬底中邻近所述闪存单元形成源极区域和漏极区域。

公开(公告)号：US06510085B1

公开(公告)日：2003-01-21

申请号：US09861031

申请日：2001-05-18

申请人： Richard Fastow ,  Sheunghee Park ,  Zhigang Wang ,  Sameer Haddad ,  Chi Chang

发明人： Richard Fastow ,  Sheunghee Park ,  Zhigang Wang ,  Sameer Haddad ,  Chi Chang

IPC分类号： G11C1604

CPC分类号： G11C16/3409 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3404

摘要： Methods of programming and soft programming short channel NOR flash memory cells that reduce the programming currents and column leakages during both programming and soft programming while maintaining fast programming speeds. During programming, a voltage of between 7 and 10 volts is applied to the control gate, a voltage of between 4 and 6 volts; is applied to the drain, a voltage of between 0.5 and 2.0 volts is applied to the source and a voltage of between minus 2 and minus 0.5 volts is applied to the substrate of the selected cell to be programmed. During soft programming, a voltage of between 0.5 and 4.5 volts is applied to the control gates, between 4 and 5.5 volts is applied to the drains, between 0.5 and 2 volts is applied to the sources and between minus 2.0 and minus 0.5 volts is applied to the substrates of the memory cells.

摘要翻译： 编程和软编程短节目NOR闪存单元的方法，可在编程和软编程期间减少编程电流和列泄漏，同时保持快速的编程速度。 在编程期间，7至10伏之间的电压施加到控制栅极，电压在4和6伏之间; 施加到漏极，将0.5至2.0伏之间的电压施加到源极，并且在所述要编程的所选择的单元的衬底之间施加负2和负0.5伏之间的电压。 在软编程期间，向控制栅极施加0.5至4.5伏之间的电压，在漏极之间施加4至5.5伏之间的电压，施加0.5至2伏之间的电压，并施加负2.0至负0.5伏之间 到存储单元的基板。

公开(公告)号：US06444539B1

公开(公告)日：2002-09-03

申请号：US09784892

申请日：2001-02-15

申请人： Yu Sun ,  Angela T. Hui ,  Yue-Song He ,  Tatsuya Kajita ,  Mark Chang ,  Chi Chang ,  Hung-Sheng Chen

发明人： Yu Sun ,  Angela T. Hui ,  Yue-Song He ,  Tatsuya Kajita ,  Mark Chang ,  Chi Chang ,  Hung-Sheng Chen

IPC分类号： H01L2176

CPC分类号： H01L21/7621 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/76232

摘要： A semiconductor apparatus and method for producing shallow trench isolation. The method includes the steps providing a semiconductor substrate member fabricated having a thin barrier oxide layer on which are fabricated a plurality of spaced apart silicon nitride pads. The regions between the spaced apart nitride pads delineate U-shaped regions for forming shallow isolation trenches and are layered with silicon oxide and polysilicon. The U-shaped regions provide a buffer region of oxide and polysilicon material adjacent opposing silicon nitride pads that prevent erosion of the nitride during etch formation of the isolation trench. The polysilicon is further etched to form a wider, second U-shaped region having sloped sidewalls that provide opposing spacer-forming buffer material that facilitates forming a V-shaped isolation trench region into the semiconductor substrate member a predetermined depth without eroding the silicon nitride pads. The V-shaped trench is subsequently filled with silicon dioxide that is grown by a hot thermal oxide process. The upper portion of the V-shaped isolation trench may be further filled with deposited silicon dioxide followed by a chemical mechanical polishing process.

摘要翻译： 一种用于产生浅沟槽隔离的半导体装置和方法。 该方法包括提供制造具有薄的阻挡氧化物层的半导体衬底构件的步骤，在其上制造多个间隔开的氮化硅衬垫。 间隔开的氮化物衬垫之间的区域划定用于形成浅隔离沟槽的U形区域并且与氧化硅和多晶硅层叠。 U形区域提供邻近相对的氮化硅焊盘的氧化物和多晶硅材料的缓冲区，其在隔离沟槽的蚀刻形成期间防止氮化物的侵蚀。 多晶硅被进一步蚀刻以形成更宽的第二U形区域，其具有倾斜的侧壁，其提供相对的间隔物形成缓冲材料，其有利于在不侵蚀氮化硅焊盘的情况下在半导体衬底构件中形成预定深度的V形隔离沟槽区域 。 随后，V形沟槽填充二氧化硅，二氧化硅通过热的热氧化工艺生长。 V形隔离沟槽的上部可以进一步填充沉积的二氧化硅，随后进行化学机械抛光工艺。

公开(公告)号：US06252276B1

公开(公告)日：2001-06-26

申请号：US09377183

申请日：1999-08-19

申请人： Mark Ramsbey ,  Sameer Haddad ,  Vei-Han Chan ,  Yu Sun ,  Chi Chang

发明人： Mark Ramsbey ,  Sameer Haddad ,  Vei-Han Chan ,  Yu Sun ,  Chi Chang

IPC分类号： H01L2978

CPC分类号： H01L21/28202 ,  H01L21/28273 ,  H01L29/518 ,  H01L29/66825

摘要： Methods and arrangements are provided for introducing nitrogen into a tunnel oxide layer within a stacked gate structure of a non-volatile memory cell. The nitrogen is advantageously introduced into only a select portion of the tunnel oxide, preferably nearer the source region of the memory cell. This prevents the unwanted or residual nitrogen from detrimentally affecting other devices within the semiconductor integrated circuit.

摘要翻译： 提供了将氮气引入非易失性存储单元的堆叠栅极结构内的隧道氧化物层中的方法和装置。 有利地，氮被引入隧道氧化物的选择部分，优选地更接近存储器单元的源极区域。 这防止了不需要的或残留的氮气有害地影响半导体集成电路内的其它器件。

公开(公告)号：US6160317A

公开(公告)日：2000-12-12

申请号：US336057

申请日：1999-06-18

申请人： Yu Sun ,  Chi Chang ,  Mark T. Ramsbey

发明人： Yu Sun ,  Chi Chang ,  Mark T. Ramsbey

IPC分类号： H01L21/8247 ,  H01L27/105 ,  H01L27/088

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11536

摘要： The present invention provides a semiconductor device and a method for providing such a semiconductor device which allows a field oxide etch while minimizing the damage to the silicon. This method is particularly useful for smaller semiconductor devices, for example, such as a semiconductor device utilizing core source spacing less than 0.4 microns. A method according to the present invention for providing a semiconductor device comprises the steps of depositing a first spacer oxide layer over a core area and a peripheral area of a semiconductor device; etching the first spacer oxide layer at the source side of core cell area; depositing a second spacer oxide layer over the core area and the peripheral area, and etching the first and second spacer oxide layers over the peripheral area only.

摘要翻译： 本发明提供了一种用于提供这种半导体器件的半导体器件和方法，其允许场氧化物蚀刻同时最小化对硅的损害。 该方法对于较小的半导体器件特别有用，例如，诸如利用芯源间距小于0.4微米的半导体器件。 根据本发明的用于提供半导体器件的方法包括以下步骤：在半导体器件的芯区域和周边区域上沉积第一间隔氧化物层; 在核心区域的源极处蚀刻第一间隔氧化物层; 在芯区域和外围区域上沉积第二间隔氧化物层，并且仅在周边区域上蚀刻第一和第二间隔氧化物层。

公开(公告)号：US6080639A

公开(公告)日：2000-06-27

申请号：US199265

申请日：1998-11-25

申请人： Richard J. Huang ,  Chi Chang

发明人： Richard J. Huang ,  Chi Chang

IPC分类号： H01L21/316 ,  H01L21/762 ,  H01L21/8247 ,  H01L21/76 ,  H01L21/4763

CPC分类号： H01L27/11521 ,  H01L21/02129 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02362 ,  H01L21/31625 ,  H01L21/76202 ,  H01L21/76235

摘要： Void formation is avoided without thermal treatment by a gap filling between electrically conductive elements such as stacked gates which are formed atop of isolation regions, with an oxide layer using a HDP technique. The oxide layer is doped with phosphorus to getter mobile ionic contaminants.

摘要翻译： 通过在形成于隔离区域顶部的层叠栅极之间的导电元件之间的间隙填充，使用HDP技术的氧化物层，避免了空隙形成。 氧化物层掺杂磷以吸收移动离子污染物。

公开(公告)号：US5972751A

公开(公告)日：1999-10-26

申请号：US143090

申请日：1998-08-28

申请人： Mark Ramsbey ,  Sameer Haddad ,  Vei-Han Chan ,  Yu Sun ,  Chi Chang

发明人： Mark Ramsbey ,  Sameer Haddad ,  Vei-Han Chan ,  Yu Sun ,  Chi Chang

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/51

CPC分类号： H01L21/28202 ,  H01L21/28273 ,  H01L29/518 ,  H01L29/66825

摘要： Methods and arrangements are provided for introducing nitrogen into a tunnel oxide layer within a stacked gate structure of a non-volatile memory cell. The nitrogen is advantageously introduced into only a select portion of the tunnel oxide, preferably nearer the source region of the memory cell. This prevents the unwanted or residual nitrogen from detrimentally affecting other devices within the semiconductor integrated circuit.

摘要翻译： 提供了将氮气引入非易失性存储单元的堆叠栅极结构内的隧道氧化物层中的方法和装置。 有利地，氮被引入隧道氧化物的选择部分，优选地更接近存储器单元的源极区域。 这防止了不需要的或残留的氮气有害地影响半导体集成电路内的其它器件。

公开(公告)号：US5852582A

公开(公告)日：1998-12-22

申请号：US801305

申请日：1997-02-18

申请人： Lee E. Cleveland ,  Yuan Tang ,  Jonathan Su ,  Chi Chang ,  Chung K. Chang

发明人： Lee E. Cleveland ,  Yuan Tang ,  Jonathan Su ,  Chi Chang ,  Chung K. Chang

IPC分类号： G11C16/28 ,  G11C16/32 ,  G11C16/34 ,  G11C13/00

CPC分类号： G11C16/3431 ,  G11C16/28 ,  G11C16/32 ,  G11C16/3418

摘要： A timing apparatus for monitoring when a memory array in a non-volatile storage device needs to be refreshed includes a programmable semiconductor device and detecting means for detecting when the amount of charge on the programmable semiconductor device has diminished to at most a threshold amount. In one embodiment, the programmable semiconductor device is a floating gate transistor programmed by adding charge to the floating gate. The detecting means monitors the I.sub.DS current of the transistor and determines an array refresh time when more than a negligible amount of I.sub.DS current is detected.

摘要翻译： 用于监视非易失性存储装置中的存储器阵列何时需要刷新的定时装置包括可编程半导体器件和检测装置，用于检测可编程半导体器件上的电荷量何时已降至至多阈值量。 在一个实施例中，可编程半导体器件是通过向浮动栅极增加电荷而编程的浮栅晶体管。 检测装置监视晶体管的IDS电流，并且当检测到多于可忽略的IDS电流量时，确定阵列刷新时间。

公开(公告)号：US08742486B2

公开(公告)日：2014-06-03

申请号：US11702846

申请日：2007-02-05

申请人： Wei Zheng ,  Chi Chang ,  Unsoon Kim

发明人： Wei Zheng ,  Chi Chang ,  Unsoon Kim

IPC分类号： H01L29/68

CPC分类号： H01L29/792 ,  H01L21/823418 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/7923

摘要： An embodiment of the present invention is directed to a memory cell. The memory cell includes a first trench formed in a semiconductor substrate and a second trench formed in said semiconductor substrate adjacent to said first trench. The first trench and the second trench each define a first side wall and a second sidewall respectively. The memory cell further includes a first storage element formed on the first sidewall of the first trench and a second storage element formed on the second sidewall of the second trench.

摘要翻译： 本发明的实施例涉及存储单元。 存储单元包括形成在半导体衬底中的第一沟槽和形成在与所述第一沟槽相邻的所述半导体衬底中的第二沟槽。 第一沟槽和第二沟槽分别限定第一侧壁和第二侧壁。 存储单元还包括形成在第一沟槽的第一侧壁上的第一存储元件和形成在第二沟槽的第二侧壁上的第二存储元件。

公开(公告)号：US08266470B2

公开(公告)日：2012-09-11

申请号：US12564907

申请日：2009-09-22

申请人： Ching-Yen Wu ,  Chi Chang

发明人： Ching-Yen Wu ,  Chi Chang

IPC分类号： G06F1/04 ,  G06F1/00

CPC分类号： G06F1/08 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： A clock generating device, method thereof and a computer system using the same are provided. The clock generating device includes a PLL module and a tuning module. The PLL module receives a reference clock signal, and generates an output clock signal as a basic clock of a computer system according to a phase difference between a reference clock signal and a feedback signal. The PLL module includes a frequency divider adjusting an intrinsic frequency dividing ratio according to a control signal and performs a frequency dividing processing on the output clock signal to generate a feedback signal. The tuning module coupled with the PLL module generates the control signal according to a VID of a CPU and one of the feedback signal and the reference clock. Therefore, the operation frequency of the components serving the output clock signal as the basic frequency in the computer system can be synchronously tuned.

摘要翻译： 提供了一种时钟发生装置及其方法以及使用其的计算机系统。 时钟发生装置包括PLL模块和调谐模块。 PLL模块接收参考时钟信号，并根据参考时钟信号和反馈信号之间的相位差产生输出时钟信号作为计算机系统的基本时钟。 PLL模块包括根据控制信号调整固有分频比的分频器，并对输出时钟信号进行分频处理以产生反馈信号。 与PLL模块耦合的调谐模块根据CPU的VID和反馈信号和参考时钟之一产生控制信号。 因此，可以同步调整作为计算机系统中的基本频率的输出时钟信号的组件的操作频率。