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    METHODS OF FORMING METAL OXIDE
    31.
    发明申请
    METHODS OF FORMING METAL OXIDE 审中-公开
    形成金属氧化物的方法

    公开(公告)号：US20150056798A1

    公开(公告)日：2015-02-26

    申请号：US14506235

    申请日：2014-10-03

    Applicant: Micron Technology, Inc.

    Inventor： Noel Rocklein ,  Durai Ramaswamy ,  Dale W. Collins ,  Swapnil Lengade ,  Srividya Krishnamurthy ,  Mark S. Korber

    IPC: H01L45/00 ,  H01B1/08 ,  H01L21/283

    CPC classification number: H01L45/1641 ,  H01B1/08 ,  H01L21/283 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147

    Abstract: Some embodiments include methods of forming memory cells. Metal oxide may be deposited over a first electrode, with the deposited metal oxide having a relatively low degree of crystallinity. The degree of crystallinity within the metal oxide may be increased after the deposition of the metal oxide. A dielectric material may be formed over the metal oxide, and a second electrode may be formed over the dielectric material. The degree of crystallinity may be increased with a thermal treatment. The thermal treatment may be conducted before, during, and/or after formation of the dielectric material.

    Abstract translation: 一些实施例包括形成存储器单元的方法。 金属氧化物可以沉积在第一电极上，沉积的金属氧化物具有相对低的结晶度。 在沉积金属氧化物之后，金属氧化物内的结晶度可以增加。 可以在金属氧化物上形成电介质材料，并且可以在电介质材料上形成第二电极。 可以通过热处理来提高结晶度。 热处理可以在形成介电材料之前，期间和/或之后进行。

    Integrated circuitry comprising a memory array comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells
    33.
    发明授权
    Integrated circuitry comprising a memory array comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells 有权

    公开(公告)号：US11792983B2

    公开(公告)日：2023-10-17

    申请号：US17068430

    申请日：2020-10-12

    Applicant: Micron Technology, Inc.

    Inventor： Daniel Billingsley ,  Jordan D. Greenlee ,  John D. Hopkins ,  Yongjun Jeff Hu ,  Swapnil Lengade

    IPC: H01L21/31 ,  H10B43/27 ,  H01L21/311 ,  H10B41/27

    CPC classification number: H10B43/27 ,  H01L21/31111 ,  H10B41/27

    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming an upper stack directly above a lower stack. The lower stack comprises vertically-alternating lower-first-tiers and lower-second-tiers. The upper stack comprises vertically-alternating upper-first-tiers and upper-second-tiers. Lower channel openings extend through the lower-first-tiers and the lowers-second-tiers. The lower channel openings have sacrificial material therein. An upper of the lower-first-tiers or a lower of the upper-first-tiers comprises non-stoichiometric silicon nitride comprising (a) or (b), where (a): a nitrogen-to-silicon atomic ratio greater than 1.33 and less than 1.5; and (b): a nitrogen-to-silicon atomic ratio greater than or equal to 1.0 and less than 1.33. A higher of the upper-first-tiers that is above said lower upper-first-tier comprises silicon nitride not having either the (a) or the (b). Upper channel openings are etched through the upper-first-tiers and the upper-second-tiers to stop on said upper lower-first-tier or said lower upper-first-tier. After the stop, the sacrificial material is removed from the lower channel openings and form channel-material strings in the upper and lower channel openings. Other embodiments, including structure independent of method, are disclosed.

    SEMICONDUCTOR DEVICES INCLUDING LINERS, AND RELATED SYSTEMS
    35.
    发明申请
    SEMICONDUCTOR DEVICES INCLUDING LINERS, AND RELATED SYSTEMS 审中-公开

    公开(公告)号：US20190097133A1

    公开(公告)日：2019-03-28

    申请号：US16202379

    申请日：2018-11-28

    Applicant: Micron Technology, Inc.

    Inventor： Dale W. Collins ,  Andrea Gotti ,  F. Daniel Gealy ,  Tuman E. Allen ,  Swapnil Lengade

    IPC: H01L45/00 ,  H01L27/24

    Abstract: A semiconductor structure includes a plurality of stack structures overlying a substrate. Each stack structure includes a first chalcogenide material over a conductive material overlying the substrate, an electrode over the first chalcogenide material, a second chalcogenide material over the electrode, a liner on sidewalls of at least one of the first chalcogenide material or the second chalcogenide material, and a dielectric material over and in contact with sidewalls of the electrode and in contact with the liner. Related semiconductor devices and systems, methods of forming the semiconductor structure, semiconductor device, and systems, and methods of forming the liner in situ are disclosed.

    Phase change memory stack with treated sidewalls
    36.
    发明授权
    Phase change memory stack with treated sidewalls 有权

    公开(公告)号：US10224479B2

    公开(公告)日：2019-03-05

    申请号：US15882666

    申请日：2018-01-29

    Applicant: Micron Technology, Inc.

    Inventor： Tsz W. Chan ,  Yongjun Jeff Hu ,  Swapnil Lengade ,  Shu Qin ,  Everett Allen McTeer

    IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24

    Abstract: Memory devices and methods for fabricating memory devices have been disclosed. One such method includes forming the memory stack out of a plurality of elements. An adhesion species is formed on at least one sidewall of the memory stack wherein the adhesion species has a gradient structure that results in the adhesion species intermixing with an element of the memory stack to terminate unsatisfied atomic bonds of the element. The gradient structure further comprises a film of the adhesion species on an outer surface of the at least one sidewall. A dielectric material is implanted into the film of the adhesion species to form a sidewall liner.

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