公开(公告)号：US11984382B2

公开(公告)日：2024-05-14

申请号：US17492185

申请日：2021-10-01

Applicant: Micron Technology, Inc.

Inventor： Pengyuan Zheng ,  David Ross Economy ,  Yongjun J. Hu ,  Kent H. Zhuang ,  Robert K. Grubbs

IPC: H01L23/373 ,  H01L21/02 ,  H01L21/768 ,  H01L23/535

CPC classification number: H01L23/3736 ,  H01L21/02186 ,  H01L21/0234 ,  H01L21/768 ,  H01L23/535

Abstract: Methods, systems, and devices related to a memory device with a thermal barrier are described. The thermal barrier (e.g., a low density thermal barrier) may be positioned between an access line (e.g., a digit line or a word line) and a cell component. The thermal barrier may be formed on the surface of a barrier material by applying a plasma treatment to the barrier material. The thermal barrier may have a lower density than the barrier material and may be configured to thermally insulate the cell component from thermal energy generated in the memory device, among other benefits.

公开(公告)号：US11705500B2

公开(公告)日：2023-07-18

申请号：US17180312

申请日：2021-02-19

Applicant: Micron Technology, Inc.

Inventor： David Ross Economy ,  Rita J. Klein ,  Jordan D. Greenlee ,  John Mark Meldrim ,  Brenda D. Kraus ,  Everett A. McTeer

IPC: H01L29/49 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11565 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27 ,  H10B41/35 ,  H10B43/35

CPC classification number: H01L29/4966 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27 ,  H10B41/35 ,  H10B43/35

Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and control gate levels. Channel material extends vertically along the stack. The control gate levels comprising conductive regions. The conductive regions include at least three different materials. Charge-storage regions are adjacent the control gate levels. Charge-blocking regions are between the charge-storage regions and the conductive regions.

公开(公告)号：US11646206B2

公开(公告)日：2023-05-09

申请号：US17101950

申请日：2020-11-23

Applicant: Micron Technology, Inc.

Inventor： David Ross Economy ,  Brian Beatty ,  John Mark Meldrim ,  Yongjun Jeff Hu ,  Jordan D. Greenlee

IPC: H01L21/02 ,  C23C16/28 ,  C01G41/00

CPC classification number: H01L21/02645 ,  C01G41/00 ,  C23C16/28 ,  H01L21/0257 ,  C01P2006/40

Abstract: Described are methods for forming a multilayer conductive structure for semiconductor devices. A seed layer is formed comprising a metal and an additional constituent that in combination with the metal inhibits nucleation of a fill layer of the metal formed over the seed layer. Tungsten may be doped or alloyed with silicon to form the seed layer, with a tungsten fill being formed over the seed layer.

公开(公告)号：US11456208B2

公开(公告)日：2022-09-27

申请号：US16990463

申请日：2020-08-11

Applicant: Micron Technology, Inc.

Inventor： Sidhartha Gupta ,  David Ross Economy ,  Richard J. Hill ,  Kyle A. Ritter ,  Naveen Kaushik

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/11582 ,  H01L27/11556

Abstract: A method of forming an apparatus includes forming pillar structures extending vertically through a first isolation material, forming conductive lines operatively coupled to the pillar structures, forming dielectric structures overlying the conductive lines, and forming air gaps between neighboring conductive lines. The air gaps are laterally adjacent to the conductive lines with a portion of the air gaps extending above a plane of an upper surface of the laterally adjacent conductive lines and a portion of the air gaps extending below a plane of a lower surface of the laterally adjacent conductive lines. Apparatuses, memory devices, methods of forming a memory device, and electronic systems are also disclosed.

公开(公告)号：US11189662B2

公开(公告)日：2021-11-30

申请号：US16746645

申请日：2020-01-17

Applicant: Micron Technology, Inc.

Inventor： David Ross Economy ,  Andrew Leslie Beemer

IPC: H01L47/00 ,  H01L27/24 ,  H01L21/768 ,  H01L21/321 ,  H01L23/522 ,  H01L45/00 ,  H01L23/532 ,  H01L23/528

Abstract: Methods, systems, and devices for via formation in a memory device are described. A memory cell stack for a memory array may be formed. In some examples, the memory cell stack may comprise a storage element. A via may also be formed in an area outside of the memory array, and the via may protrude from a material that surrounds the via. A material may then be formed above the memory cell stack and also above the via, and the top surface of the barrier material may be planarized until at least a portion of the via is exposed. A subsequently formed material may thereby be in direct contact with the top of the via, while a portion of the initially formed material may remain above the memory cell stack.

公开(公告)号：US20210312978A1

公开(公告)日：2021-10-07

申请号：US17236700

申请日：2021-04-21

Applicant: Micron Technology, Inc.

Inventor： David Ross Economy ,  Stephen W. Russell

IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24

Abstract: Methods, systems, and devices for access line grain modulation in a memory device are described. A memory cell stack in a cross-point memory array may be formed. In some examples, the memory cell stack may comprise a storage element. A barrier material may be formed above the memory cell stack. The barrier material may initially have an undulating top surface. In some cases, the top surface of the barrier material may be planarized. After the top surface of the barrier material is planarized, a metal layer for an access line may be formed on the top surface of the barrier material. Planarizing the top surface of the barrier material may impact the grain size of the metal layer. In some cases, planarizing the top surface of the barrier material may decrease the resistivity of access lines formed from the metal layer and thus increase current delivery throughout the memory device.

公开(公告)号：US20210225937A1

公开(公告)日：2021-07-22

申请号：US16746645

申请日：2020-01-17

Applicant: Micron Technology, Inc.

Inventor： David Ross Economy ,  Andrew Leslie Beemer

IPC: H01L27/24 ,  H01L21/321 ,  H01L45/00 ,  H01L23/528 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522

Abstract: Methods, systems, and devices for via formation in a memory device are described. A memory cell stack for a memory array may be formed. In some examples, the memory cell stack may comprise a storage element. A via may also be formed in an area outside of the memory array, and the via may protrude from a material that surrounds the via. A material may then be formed above the memory cell stack and also above the via, and the top surface of the barrier material may be planarized until at least a portion of the via is exposed. A subsequently formed material may thereby be in direct contact with the top of the via, while a portion of the initially formed material may remain above the memory cell stack.

公开(公告)号：US10964621B2

公开(公告)日：2021-03-30

申请号：US16400927

申请日：2019-05-01

Applicant: Micron Technology, Inc.

Inventor： David Ross Economy ,  Pengyuan Zheng

IPC: H01L21/02 ,  H01L21/768 ,  H01L23/535 ,  H01L23/373

Abstract: Methods, systems, and devices for a memory device with a high resistivity thermal barrier are described. In some examples a barrier material may be positioned over a memory cell region, an oxide region, and/or a through-silicon via (TSV). The barrier may include a first region above the memory cell region and a second region above the TSV. A process, such as a plasma treatment, may be applied to the barrier, which may result in the first and second regions having different thermal resistivities (e.g., different densities). Accordingly, due to the different thermal resistivities, the memory cells may be thermally insulated from thermal energy generated in the memory device.

公开(公告)号：US10957775B2

公开(公告)日：2021-03-23

申请号：US16458400

申请日：2019-07-01

Applicant: Micron Technology, Inc.

Inventor： David Ross Economy ,  Rita J. Klein ,  Jordan D. Greenlee ,  John Mark Meldrim ,  Brenda D. Kraus ,  Everett A. McTeer

IPC: H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L29/49

Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and control gate levels. Channel material extends vertically along the stack. The control gate levels comprising conductive regions. The conductive regions include at least three different materials. Charge-storage regions are adjacent the control gate levels. Charge-blocking regions are between the charge-storage regions and the conductive regions.

公开(公告)号：US20200350225A1

公开(公告)日：2020-11-05

申请号：US16400927

申请日：2019-05-01

Applicant: Micron Technology, Inc.

Inventor： David Ross Economy ,  Pengyuan Zheng

IPC: H01L23/373 ,  H01L21/02 ,  H01L23/535 ,  H01L21/768

Abstract: Methods, systems, and devices for a memory device with a high resistivity thermal barrier are described. In some examples a barrier material may be positioned over a memory cell region, an oxide region, and/or a through-silicon via (TSV). The barrier may include a first region above the memory cell region and a second region above the TSV. A process, such as a plasma treatment, may be applied to the barrier, which may result in the first and second regions having different thermal resistivities (e.g., different densities). Accordingly, due to the different thermal resistivities, the memory cells may be thermally insulated from thermal energy generated in the memory device.