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    APPARATUSES INCLUDING TRANSISTORS, AND RELATED METHODS, MEMORY DEVICES, AND ELECTRONIC SYSTEMS
    31.
    发明申请
    APPARATUSES INCLUDING TRANSISTORS, AND RELATED METHODS, MEMORY DEVICES, AND ELECTRONIC SYSTEMS 有权

    公开(公告)号：US20210351182A1

    公开(公告)日：2021-11-11

    申请号：US16869339

    申请日：2020-05-07

    Applicant: Micron Technology, Inc.

    Inventor： Litao Yang ,  Srinivas Pulugurtha ,  Haitao Liu

    IPC: H01L27/108 ,  H01L23/522 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L29/66

    Abstract: An apparatus comprises a first conductive structure and at least one transistor in electrical communication with the first conductive structure. The at least one transistor comprises a lower conductive contact coupled to the first conductive structure and a split-body channel on the lower conductive contact. The split-body channel comprises a first semiconductive pillar and a second semiconductive pillar horizontally neighboring the first semiconductive pillar. The at least one transistor also comprises a gate structure horizontally interposed between the first semiconductive pillar and the second semiconductive pillar of the split-body channel and an upper conductive contact vertically overlying the gate structure and coupled to the split-body channel. Portions of the gate structure surround three sides of each of the first semiconductive pillar and the second semiconductive pillar. Memory devices, electronic systems, and methods of forming the apparatus are also disclosed.

    Integrated Assemblies Having Shield Lines Between Digit Lines, and Methods of Forming Integrated Assemblies
    32.
    发明申请
    Integrated Assemblies Having Shield Lines Between Digit Lines, and Methods of Forming Integrated Assemblies 有权

    公开(公告)号：US20210327883A1

    公开(公告)日：2021-10-21

    申请号：US17362790

    申请日：2021-06-29

    Applicant: Micron Technology, Inc.

    Inventor： Sanh D. Tang ,  Srinivas Pulugurtha ,  Richard J. Hill ,  Yunfei Gao ,  Nicholas R. Tapias ,  Litao Yang ,  Haitao Liu

    IPC: H01L27/108

    Abstract: Some embodiments include an integrated assembly having digit lines which extend along a first direction, and which are spaced from one another by intervening regions. Each of the intervening regions has a first width along a cross-section. Pillars extend upwardly from the digit lines; and the pillars include transistor channel regions extending vertically between upper and lower source/drain regions. Storage elements are coupled with the upper source/drain regions. Wordlines extend along a second direction which crosses the first direction. The wordlines include gate regions adjacent the channel regions. Shield lines are within the intervening regions and extend along the first direction. The shield lines may be coupled with at least one reference voltage node. Some embodiments include methods of forming integrated assemblies.

    SEMICONDUCTOR DEVICES INCLUDING VERTICAL MEMORY CELLS AND METHODS OF FORMING SAME
    37.
    发明申请
    SEMICONDUCTOR DEVICES INCLUDING VERTICAL MEMORY CELLS AND METHODS OF FORMING SAME 有权
    包括垂直存储器单元的半导体器件及其形成方法

    公开(公告)号：US20150129955A1

    公开(公告)日：2015-05-14

    申请号：US14075480

    申请日：2013-11-08

    Applicant: Micron Technology, Inc.

    Inventor： Wolfgang Mueller ,  Sanh D. Tang ,  Sourabh Dhir ,  Srinivas Pulugurtha

    IPC: H01L29/78 ,  H01L27/105 ,  H01L29/66

    CPC classification number: H01L29/7827 ,  G11C11/40 ,  H01L27/0207 ,  H01L27/1052 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10885 ,  H01L27/10891 ,  H01L29/66666

    Abstract: A semiconductor device may include a memory array including vertical memory cells connected to a digit line, word lines, and a body connection line. A row or column of the memory array may include one or more pillars connected to the body connection line. A voltage may be applied to the body connection line through at least one pillar connected to the body connection line. Application of the voltage to the body connection line may reduce floating body effects. Methods of forming a connection between at least one pillar and a voltage supply are disclosed. Semiconductor devices including such connections are also disclosed.

    Abstract translation: 半导体器件可以包括存储器阵列，其包括连接到数字线，字线和主体连接线的垂直存储器单元。 存储器阵列的行或列可以包括连接到主体连接线的一个或多个支柱。 可以通过连接到主体连接线的至少一个支柱将电压施加到主体连接线。 施加电压到身体连接线可能会减少浮体效应。 公开了形成至少一个柱和电压源之间的连接的方法。 还公开了包括这种连接的半导体器件。

    VERTICAL ACCESS DEVICE AND APPARATUSES HAVING A BODY CONNECTION LINE, AND RELATED METHOD OF OPERATING THE SAME
    38.
    发明申请
    VERTICAL ACCESS DEVICE AND APPARATUSES HAVING A BODY CONNECTION LINE, AND RELATED METHOD OF OPERATING THE SAME 有权
    具有身体连接线的垂直存取装置和装置及其相关操作方法

    公开(公告)号：US20140247674A1

    公开(公告)日：2014-09-04

    申请号：US13782792

    申请日：2013-03-01

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Kamal M. Karda ,  Rajesh N. Gupta ,  Srinivas Pulugurtha ,  Chandra V. Mouli ,  Wolfgang Mueller

    IPC: H01L29/78 ,  G11C11/40

    CPC classification number: H01L29/7827 ,  G11C11/40 ,  H01L27/0207 ,  H01L27/1052 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10885 ,  H01L27/10891 ,  H01L29/66666

    Abstract: Methods, apparatuses, and systems for providing a body connection to a vertical access device. The vertical access device may include a digit line extending along a substrate to a digit line contact pillar, a body connection line extending along the substrate to a body connection line contact pillar, a body region disposed on the body connection line, an electrode disposed on the body region, and a word line extending to form a gate to the body region. A method for operation includes applying a first voltage to the body connection line, and applying a second voltage to the word line to cause a conductive channel to form through the body region. A memory cell array may include a plurality of vertical access devices.

    Abstract translation: 用于向垂直存取装置提供身体连接的方法，装置和系统。 垂直进入装置可以包括沿着基板延伸到数字线接触柱的数字线，沿着基板延伸到主体连接线接触柱的主体连接线，设置在主体连接线上的主体区域，设置在主体连接线上的电极 身体区域和延伸以形成到身体区域的门的字线。 一种操作方法包括：将第一电压施加到身体连接线，以及向该字线施加第二电压，以使导电通道通过身体区域形成。 存储单元阵列可以包括多个垂直存取装置。

    ASYMMETRIC TRANSISTOR DEVICES
    39.
    发明公开
    ASYMMETRIC TRANSISTOR DEVICES 审中-公开

    公开(公告)号：US20240284663A1

    公开(公告)日：2024-08-22

    申请号：US18440348

    申请日：2024-02-13

    Applicant: Micron Technology, Inc.

    Inventor： Srinivas Pulugurtha ,  Dan Mihai Mocuta

    IPC: H10B12/00 ,  G11C11/4091

    CPC classification number: H10B12/50 ,  G11C11/4091

    Abstract: A variety of applications can include an apparatus having one or more pairs of transistors sharing a common source region that provide asymmetric transistor devices. The drains of the transistors of a pair sharing a common source region can be structured with the source junction depth being shallower than the drain junction depth of the drain region of at least one of the transistors of the pair. Tilted implantation can be used to extend a drain junction depth beyond the distance of the source junction depth by implanting additional dopants. The extension of the drain junction depth can be accomplished without additional masks being used in processing to dope only a drain region and skip doping on a corresponding source region.

    Integrated assemblies, and methods of forming integrated assemblies
    40.
    发明授权
    Integrated assemblies, and methods of forming integrated assemblies 有权

    公开(公告)号：US11563010B2

    公开(公告)日：2023-01-24

    申请号：US16666709

    申请日：2019-10-29

    Applicant: Micron Technology, Inc.

    Inventor： Litao Yang ,  Srinivas Pulugurtha ,  Haitao Liu

    IPC: H01L27/108 ,  H01L27/06 ,  H01L21/8254 ,  H01L29/10

    Abstract: Some embodiments include an integrated assembly having an active region which contains semiconductor material. The active region includes first, second and third source/drain regions within the semiconductor material, includes a first channel region within the semiconductor material and between the first and second source/drain regions, and includes a second channel region within the semiconductor material and between the second and third source/drain regions. The semiconductor material includes at least one element selected from Group 13 of the periodic table. A digit line is electrically coupled with the second source/drain region. A first transistor gate is operatively proximate the first channel region. A second transistor gate is operatively proximate the second channel region. A first storage-element is electrically coupled with the first source/drain region. A second storage-element is electrically coupled with the third source/drain region. Some embodiments include methods of forming integrated assemblies.

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