公开(公告)号：US20250004962A1

公开(公告)日：2025-01-02

申请号：US18829713

申请日：2024-09-10

Applicant: Micron Technology, Inc.

Inventor： Eric N. Lee ,  Leonid Minz ,  Yoav Weinberg ,  Ali Feiz Zarrin Ghalam ,  Luigi Pilolli

IPC: G06F13/30 ,  G06F13/16

Abstract: A memory device includes a memory array and processing logic, operatively coupled with the memory array, to perform operations including causing a data transfer across an interface bus to be suspended by toggling a logical level of a control pin from a first level that activates the data transfer to a second level that suspends the data transfer, and causing the data transfer to resume by toggling the logical level of the control pin from the second level to the first level.

公开(公告)号：US20240429904A1

公开(公告)日：2024-12-26

申请号：US18826526

申请日：2024-09-06

Applicant: Micron Technology, Inc.

Inventor： Leon Zlotnik ,  Leonid Minz ,  Yoav Weinberg

IPC: H03K3/037 ,  G11C19/28

Abstract: A plurality of flip-flops of an integrated circuit (IC) (e.g., an ASIC) are electrically connected in a predefined series. The scan input gate of any give flip-flop in the predefined series is electrically connected to one of a Q output gate or a Q-bar output gate of an adjacent flip-flop in the predefined series. A reset operation for the IC occurs by feeding a bit string of identical bits (e.g., all zeros) through the scan input gate of a first flip-flop of the plurality of flip-flops to reset the plurality of flip-flops without the need for resetting circuitry and accompanying power savings for the IC.

公开(公告)号：US12073121B2

公开(公告)日：2024-08-27

申请号：US18048292

申请日：2022-10-20

Applicant: Micron Technology, Inc.

Inventor： Chandrakanth Rapalli ,  Yoav Weinberg ,  Tal Sharifie

IPC: G06F12/00 ,  G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0631 ,  G06F3/0673

Abstract: Methods, systems, and devices for command timer interrupt are described. In some cases, a memory system having a host-driven logical block interface may maintain a timer to measure processing of commands. For example, upon receiving a command and storing the command in a command queue, a protocol controller of the memory system may issue the command to a command controller of the memory system and initiate the timer. Upon receiving a response for the command from the command controller, the protocol controller may reset or stop the timer, depending on whether the command queue is empty. If the timer expires prior to receiving a response for the command, the protocol controller may issue an interrupt signal to the command controller.

公开(公告)号：US20240274211A1

公开(公告)日：2024-08-15

申请号：US18583510

申请日：2024-02-21

Applicant: Micron Technology, Inc.

Inventor： Yoav Weinberg ,  Evgeni Bassin

IPC: G11C29/02 ,  G11C5/14

CPC classification number: G11C29/021 ,  G11C5/144 ,  G11C29/028

Abstract: Methods, systems, and devices for voltage detection for managed memory systems are described. In some cases, a memory system may include circuitry to monitor one or more supply voltages to the memory system or voltages generated by the memory system to determine whether a voltage rises above an operational range. In some cases, an overvoltage detector may include an undervoltage detector that has been tuned or manufactured to have a higher threshold than an undervoltage detector used to determine whether a voltage has fallen below the operational range. Accordingly, the memory system may monitor a voltage using an undervoltage detector having a threshold corresponding to a lower bound or lower operation point of the operational range of the monitored voltage and an overvoltage detectors having a threshold corresponding to the upper bound or upper operational point of the operational range.

公开(公告)号：US20240134746A1

公开(公告)日：2024-04-25

申请号：US18048283

申请日：2022-10-19

Applicant: Micron Technology, Inc.

Inventor： Chandrakanth Rapalli ,  Yoav Weinberg ,  Tal Sharifie

IPC: G06F11/10

CPC classification number: G06F11/108 ,  G06F11/106

Abstract: Methods, systems, and devices for command and data path error protection are described. In some examples, a memory system may receive data units from a host device. The data units may include respective sets of parity bits, and the memory system may perform an error detection operation on the data units. A first controller of the memory system may generate a protocol unit using data (e.g., a subset of data) from the data units. The protocol unit may include a set of parity bits (e.g., a different set of parity bits), and a second controller of the memory system may perform an error detection operation on the protocol unit. The second controller of the memory system may generate a data storage unit using data (e.g., a subset of data) from the protocol unit, and may store the data unit and another set of parity bits to a memory device.

公开(公告)号：US20230395146A1

公开(公告)日：2023-12-07

申请号：US17831414

申请日：2022-06-02

Applicant: Micron Technology, Inc.

Inventor： Neil Petrie ,  Yoav Weinberg

IPC: G11C13/00

CPC classification number: G11C13/004 ,  G11C2013/0054 ,  G11C13/0038 ,  G11C13/0069

Abstract: An example apparatus include an array of memory cells. The example apparatus includes a memory controller coupled to the array. The memory controller can include an internal reference resistor. The memory controller can be configured to monitor memory characteristics for the array and the memory controller. The memory controller can be configured to trim the internal reference resistor to result in a target resistance value based on the memory characteristics.

公开(公告)号：US20230315569A1

公开(公告)日：2023-10-05

申请号：US18206398

申请日：2023-06-06

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer ,  Nadav Grosz ,  Lance W. Dover ,  Yoav Weinberg

IPC: G06F11/10 ,  G06F11/07 ,  G06F11/30 ,  G06F12/02 ,  G06F13/42 ,  G06F12/14

CPC classification number: G06F11/1068 ,  G06F11/0772 ,  G06F11/3037 ,  G06F12/0246 ,  G06F13/4221 ,  G06F12/1408 ,  G06F2212/7201

Abstract: A storage device includes a memory storage region and a controller having a processor. The processor retrieves user data from the memory storage region using a physical block address corresponding to a logical block address (LBA), in response to a read command. The retrieved user data includes a first hash received through a host interface in a prior host data transmission. The processor further performs error correction on the user data to generate error-corrected user data. The processor further causes a cryptographic engine to produce a second hash of the error-corrected user data. The first hash is compared to the second hash associated with the error-corrected user data to determine a match result. A notification is generated in response to the match result.

公开(公告)号：US20230195358A1

公开(公告)日：2023-06-22

申请号：US17556080

申请日：2021-12-20

Applicant: Micron Technology, Inc.

Inventor： Eyal En Gad ,  Mustafa N. Kaynak ,  Sivagnanam Parthasarathy ,  Yoav Weinberg

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: A memory device having a bit-flipping decoder. The decoder having a plurality of circuits operatable to perform parallel computation to decode a codeword according to a plurality of columns of a parity matrix. The decoder is configured to provide columns of the parity matrix for processing in the plurality of circuits in an order where columns processed concurrently by the plurality of circuits in pipeline stages include no more than one parity column of the parity matrix.

公开(公告)号：US11636904B2

公开(公告)日：2023-04-25

申请号：US17229476

申请日：2021-04-13

Applicant: Micron Technology, Inc.

Inventor： Yoav Weinberg ,  Eric N. Lee

IPC: G11C11/40 ,  G11C16/34 ,  G11C16/20 ,  G11C7/10 ,  G11C16/32 ,  G11C16/26

Abstract: A method includes determining, via status polling at a first interval, an indicator of an almost ready status of a set of memory cells of a memory device, based on the indicator of the almost ready status, determining the set of memory cells of the memory device is almost ready to complete execution of an operation on the set of memory cells of the memory device, and responsive to determining the set of memory cells of the memory device is almost ready to complete execution of the operation, performing status polling at a second interval.

公开(公告)号：US11632132B2

公开(公告)日：2023-04-18

申请号：US17447864

申请日：2021-09-16

Applicant: Micron Technology, Inc.

Inventor： Eyal En Gad ,  Zhengang Chen ,  Sivagnanam Parthasarathy ,  Yoav Weinberg

IPC: H03M13/11 ,  H03M13/09 ,  H03M13/29 ,  H03M13/15

Abstract: A processing device in a memory system receives a request to read data from a memory device. In response to receiving the request, the processing device performs an iterative error correction process on the data, wherein at least one iteration after a first iteration in the error correction process uses a criterion that is based at least partially on a previous iteration or partial iteration, and wherein performing the iterative error correction process comprises flipping any bits in the data having an associated number of unsatisfied parity check equations that satisfies a threshold criterion associated with the previous iteration.