公开(公告)号：US20240257842A1

公开(公告)日：2024-08-01

申请号：US18405096

申请日：2024-01-05

Applicant: Micron Technology, Inc.

Inventor： Tomoharu Tanaka ,  Yoshihiko Kamata ,  Yoshiaki Fukuzumi

IPC: G11C5/14 ,  G11C5/06 ,  G11C11/4074

CPC classification number: G11C5/145 ,  G11C5/063 ,  G11C16/30

Abstract: A memory device includes an array of strings of memory cells, a local bitline coupled with a plurality of the strings of memory cells, and a sense transistor having a gate terminal coupled with the local bitline. The memory device further includes a series of transistors have a data read path between a source line and the sense transistor and between the sense transistor and a global bitline that is coupled with a page buffer. A micropump is integrated within the series of transistors. Control logic is coupled with the series of transistors and to, during a read operation of a memory cell of the array and in response to the sense transistor turning on, activate the micropump to cause a constant read current to flow between the global bitline and the source line.

公开(公告)号：US20240021219A1

公开(公告)日：2024-01-18

申请号：US17812118

申请日：2022-07-12

Applicant: Micron Technology, Inc.

Inventor： Yoshiaki Fukuzumi ,  Shuji Tanaka ,  Yoshihiko Kamata ,  Jun Fujiki ,  Tomoharu Tanaka

IPC: G11C5/06 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L29/423 ,  H01L21/28 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792

CPC classification number: G11C5/063 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  H01L23/5226 ,  H01L23/5283 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

Abstract: A microelectronic device comprises a stack structure, pillar structures, a conductive plug structure, a sense transistor, and selector transistors. The stack structure comprises a vertically alternating sequence of conductive material and insulative material, and is divided into blocks separated by dielectric slot structures. The blocks individually include sub-blocks horizontally extending in parallel with one another. The pillar structures vertically extend through one of the blocks of the stack structure. Each pillar structure of a group of the pillar structures is positioned within a different one of the sub-blocks of the one of the blocks than each other pillar structure of the group. The conductive plug structure is coupled to multiple of the pillar structures of the group of the pillar structures. The sense transistor is gated by the conductive plug structure. The selector transistors couple the sense transistor to a read source line structure and a digit line structure.

公开(公告)号：US11728263B2

公开(公告)日：2023-08-15

申请号：US17681377

申请日：2022-02-25

Applicant: Micron Technology, Inc.

Inventor： Naveen Kaushik ,  Yoshihiko Kamata ,  Richard J. Hill ,  Kyle A. Ritter ,  Tomoko Ogura Iwasaki ,  Haitao Liu

IPC: H01L23/522 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

CPC classification number: H01L23/5225 ,  H01L23/5226 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

Abstract: Some embodiments include an assembly having channel-material-structures, and having memory cells along the channel-material-structures. The memory cells include charge-storage-material. Linear-conductive-structures are vertically offset from the channel-material-structures and are electrically coupled with the channel-material-structures. Intervening regions are between the linear-conductive-structures. Conductive-shield-structures are within the intervening regions. The conductive-shield-structures are electrically coupled with a reference-voltage-source.

公开(公告)号：US11670379B2

公开(公告)日：2023-06-06

申请号：US17111751

申请日：2020-12-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshiaki Fukuzumi ,  Jun Fujiki ,  Shuji Tanaka ,  Masashi Yoshida ,  Masanobu Saito ,  Yoshihiko Kamata

IPC: G11C7/00 ,  G11C16/26 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  G11C16/04 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  G11C16/24 ,  G11C16/08 ,  H01L27/11565

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/24 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582

Abstract: Arrays of memory cells might include a data line, a source, a plurality of pass gates connected in series between the data line and the source, a plurality of unit column structures each having a respective plurality of series-connected non-volatile memory cells connected in series with a respective plurality of series-connected field-effect transistors, wherein a channel of each non-volatile memory cell of its respective plurality of series-connected non-volatile memory cells and a channel of each field-effect transistor of its respective plurality of series-connected field-effect transistors are selectively connected to one another, and a plurality of backside gate lines each connected to the second control gate of a respective pass gate of the plurality of pass gates, wherein, for each unit column structure of the plurality of unit column structures, the channel of a particular field-effect transistor of its respective plurality of field-effect transistors is capacitively coupled to the first channel of a respective pass gate of the plurality of pass gates.

公开(公告)号：US11657880B2

公开(公告)日：2023-05-23

申请号：US17861502

申请日：2022-07-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshiaki Fukuzumi ,  Jun Fujiki ,  Shuji Tanaka ,  Masashi Yoshida ,  Masanobu Saito ,  Yoshihiko Kamata

IPC: G11C7/00 ,  G11C16/26 ,  G11C16/04 ,  G11C16/10 ,  G11C11/56 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11556

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/10 ,  G11C11/5628 ,  G11C11/5671 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582

Abstract: Memory might include a plurality of series-connected non-volatile memory cells, a plurality of series-connected first field-effect transistors connected in series with the plurality of series-connected non-volatile memory cells, and a second field-effect transistor, wherein the channel of the second field-effect transistor is capacitively coupled to channels of the plurality of series-connected first field-effect transistors. The memory might further include a controller configured to cause the memory to selectively activate a selected non-volatile memory cell, activate each remaining non-volatile memory cell, increase a voltage level of the respective channel of each first field-effect transistor, selectively discharge the voltage level of the respective channel of each first field-effect transistor through the selected non-volatile memory cell, and determine whether the second field-effect transistor is activated in response to a remaining voltage level of the respective channel of each first field-effect transistor.

公开(公告)号：US20230069616A1

公开(公告)日：2023-03-02

申请号：US17591516

申请日：2022-02-02

Applicant: Micron Technology, Inc.

Inventor： Koichi Kawai ,  Yoshihiko Kamata

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/24 ,  G11C16/10 ,  G11C16/34

Abstract: A memory device includes a sense amplifier (SA) latch coupled to a sense node. A dynamic latch (DL) is connected to the SA latch and coupled to sense node. A sense line includes the sense node and is selectively connected to the SA latch, the DL, and a bit line that is coupled to a memory cell string. Control logic is coupled to the SA latch and the DL, and to: cause a pre-program verify voltage to boost the sense node; and, in response to detecting a high bit value stored in SA latch, cause a voltage to turn on set transistor(s) of DL so that a first bias voltage or a second bias voltage is stored at a latch transistor. The first bias voltage is useable for slow programming of a selected memory cell and the second bias voltage is useable for fast programming of the selected memory cell.

公开(公告)号：US20220181346A1

公开(公告)日：2022-06-09

申请号：US17557389

申请日：2021-12-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshiaki Fukuzumi ,  Jun Fujiki ,  Shuji Tanaka ,  Masashi Yoshida ,  Masanobu Saito ,  Yoshihiko Kamata

IPC: H01L27/11556 ,  G11C16/34 ,  G11C5/06 ,  G11C5/02 ,  H01L27/11582

Abstract: Arrays of memory cells might include a first upper data line, a second upper data line, a lower data line, a first pass gate selectively connected to the lower data line, a second pass gate connected to the first pass gate and selectively connected to the lower data line, a third pass gate selectively connected to the lower data line, a fourth pass gate connected to the third pass gate and selectively connected to the lower data line, unit column structures selectively connected to a respective one of the upper data lines and capacitively coupled to a first channel of a respective one of the pass gates, and control lines capacitively coupled to a second channel of a respective one of the pass gates.

公开(公告)号：US20220180938A1

公开(公告)日：2022-06-09

申请号：US17111751

申请日：2020-12-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshiaki Fukuzumi ,  Jun Fujiki ,  Shuji Tanaka ,  Masashi Yoshida ,  Masanobu Saito ,  Yoshihiko Kamata

IPC: G11C16/26 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582 ,  G11C16/24 ,  G11C16/08 ,  G11C16/04

Abstract: Arrays of memory cells might include a data line, a source, a plurality of pass gates connected in series between the data line and the source, a plurality of unit column structures each having a respective plurality of series-connected non-volatile memory cells connected in series with a respective plurality of series-connected field-effect transistors, wherein a channel of each non-volatile memory cell of its respective plurality of series-connected non-volatile memory cells and a channel of each field-effect transistor of its respective plurality of series-connected field-effect transistors are selectively connected to one another, and a plurality of backside gate lines each connected to the second control gate of a respective pass gate of the plurality of pass gates, wherein, for each unit column structure of the plurality of unit column structures, the channel of a particular field-effect transistor of its respective plurality of field-effect transistors is capacitively coupled to the first channel of a respective pass gate of the plurality of pass gates.

公开(公告)号：US20220180937A1

公开(公告)日：2022-06-09

申请号：US17111729

申请日：2020-12-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yoshiaki Fukuzumi ,  Jun Fujiki ,  Shuji Tanaka ,  Masashi Yoshida ,  Masanobu Saito ,  Yoshihiko Kamata

IPC: G11C16/26 ,  G11C16/04

Abstract: An array of memory cells might include a first data line, a second data line, a source, a capacitance selectively connected to the first data line, a string of series-connected non-volatile memory cells between the first data line and the capacitance, and a pass gate selectively connected between the second data line and the source, wherein an electrode of the capacitance is capacitively coupled to a channel of the pass gate.