公开(公告)号：US20220310189A1

公开(公告)日：2022-09-29

申请号：US17730973

申请日：2022-04-27

Applicant: Micron Technology, Inc.

Inventor： Nobuo Yamamoto ,  Donald Martin Morgan ,  Victor Wong ,  Jongtae Kwak

IPC: G11C29/42 ,  G11C29/44 ,  G11C16/10 ,  G11C16/26 ,  G11C29/20

Abstract: Methods, systems, and devices for error control for memory device are described. A memory device may be configured to perform memory management operations including error control operations. For example, a memory device may be configured to perform an error control operation on data stored in a first memory cell coupled with a source row of a memory array. The memory device may be configured to write the data to a second memory cell coupled with the target row of the memory array based on performing the error control operation on the data and determine whether the management operation is complete based at least in part on the first column address of the first memory cell. The memory device may also generate an output signal to perform the error control operation on a third memory cell coupled with the source row based on determining whether the management operation is complete.

公开(公告)号：US11322218B2

公开(公告)日：2022-05-03

申请号：US16895960

申请日：2020-06-08

Applicant: Micron Technology, Inc.

Inventor： Nobuo Yamamoto ,  Donald Martin Morgan ,  Victor Wong ,  Jongtae Kwak

IPC: G11C29/00 ,  G11C29/42 ,  G11C29/44 ,  G11C16/10 ,  G11C16/26 ,  G11C29/20

Abstract: Methods, systems, and devices for error control for memory device are described. A memory device may be configured to perform memory management operations including error control operations. For example, a memory device may be configured to perform an error control operation on data stored in a first memory cell coupled with a source row of a memory array. The memory device may be configured to write the data to a second memory cell coupled with the target row of the memory array based on performing the error control operation on the data and determine whether the management operation is complete based at least in part on the first column address of the first memory cell. The memory device may also generate an output signal to perform the error control operation on a third memory cell coupled with the source row based on determining whether the management operation is complete.

公开(公告)号：US10236052B2

公开(公告)日：2019-03-19

申请号：US15592436

申请日：2017-05-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Onegyun Na ,  Jongtae Kwak ,  Seong-Hoon Lee ,  Hoon Choi

IPC: G11C7/10 ,  G11C11/4091 ,  G11C7/06 ,  G11C7/02 ,  G11C11/4074

Abstract: A current sense amplifier may include one or more clamping circuits coupled between differential output nodes of the amplifier. The clamping circuits may be enabled during at least a portion of the time that the sense amplifier is sensing the state of a memory cell coupled to a differential input of the sense amplifier. The clamping circuits may be disabled during the time that the sense amplifier is sensing the state of a memory cell at different times in a staggered manner. The clamping circuits may be effecting in making the current sense amplifier less sensitive to noise signals.

公开(公告)号：US20190027197A1

公开(公告)日：2019-01-24

申请号：US16138517

申请日：2018-09-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Hyun Yoo Lee ,  Jongtae Kwak ,  Suryanarayana Tatapudi

IPC: G11C7/00 ,  G11C11/4093 ,  G11C11/4096 ,  G11C11/4076 ,  G06F1/12 ,  G11C19/00 ,  G11C7/10 ,  G11C11/408 ,  G11C7/22

Abstract: In an example apparatus, a command path receives read commands and provides respective control signals for each read command. The command path is configured to provide initial control signals for an initial read command responsive to a first clock edge of a clock signal of a plurality of multiphase clock signals and to further provide respective control signals for subsequent read commands responsive to receipt of the subsequent mad commands. The example apparatus further includes a read data output circuit configured to receive the control signals from the command path and further receive read data in parallel. The read data output circuit is configured to provide the read data serially responsive to the control signals.

公开(公告)号：US09571105B2

公开(公告)日：2017-02-14

申请号：US14566358

申请日：2014-12-10

Applicant: Micron Technology, Inc.

Inventor： Jongtae Kwak

IPC: H03L7/06 ,  H03L7/08 ,  G11C7/10 ,  G11C7/22 ,  H03L7/081

CPC classification number: H03L7/0802 ,  G11C7/1072 ,  G11C7/222 ,  H03L7/0814 ,  H03L7/0818

Abstract: A clock generator having a delay locked loop and a delay control circuit. The delay locked loop receives an input clock signal and adjusts an adjustable delay circuit to generate an output clock signal that is synchronized with received input clock signal. The delay control circuit coupled to the delay locked loop generates a control signal to initialize the delay measure operation to adjust the adjustable delay circuit, after comparing the phase difference of the input clock signal and the output clock signal. The delay control circuit further generates a start measure control signal to start measuring a delay applied to the measurement signal propagating through the adjustable delay circuit, and generates a stop measure control signal to stop the delay measurement of the measurement signal. The delay adjustment of the delay locked loop is then adjusted to apply the delay measurement when synchronizing the input and output clock signals.

Abstract translation: 一种具有延迟锁定环路和延迟控制电路的时钟发生器。 延迟锁定环接收输入时钟信号并调整可调延迟电路以产生与接收的输入时钟信号同步的输出时钟信号。 耦合到延迟锁定环的延迟控制电路在比较输入时钟信号和输出时钟信号的相位差之后，产生控制信号以初始化延迟测量操作以调整可调延迟电路。 延迟控制电路还产生开始测量控制信号，以开始测量延迟通过可调延迟电路传播的测量信号的延迟，并产生停止测量控制信号以停止测量信号的延迟测量。 然后调整延迟锁定环路的延迟调整，以在同步输入和输出时钟信号时应用延迟测量。

公开(公告)号：US09536591B1

公开(公告)日：2017-01-03

申请号：US15063229

申请日：2016-03-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jongtae Kwak

IPC: G11C8/00 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4093 ,  G11C5/02 ,  G11C11/4096

CPC classification number: G11C11/4076 ,  G11C5/02 ,  G11C5/025 ,  G11C7/1066 ,  G11C7/109 ,  G11C7/1093 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4096 ,  G11C29/023 ,  G11C29/028

Abstract: Apparatuses and methods are described for meeting timing and latency requirements using staggered clocking within the command path. In one example, an apparatus is disclosed that includes a timing circuit configured to provide an internal clock signal; a clock stagger circuit configured to receive the internal clock signal from the timing circuit and to generate at least one delayed internal clock signal; and a shift circuit arranged in a command decode and delay path of a command signal, coupled to the timing circuit and to the clock stagger circuit, and configured to capture the command from an external clock domain into an internal clock domain based on one or both of the internal clock signal and the delayed internal clock signal

Abstract translation: 描述了使用命令路径中交错时钟来满足定时和等待时间要求的装置和方法。 在一个示例中，公开了一种装置，其包括被配置为提供内部时钟信号的定时电路; 时钟交错电路，被配置为从定时电路接收内部时钟信号并产生至少一个延迟的内部时钟信号; 以及配置在命令信号的命令解码和延迟路径中的移位电路，耦合到定时电路和时钟交错电路，并且被配置为基于一个或两者从外部时钟域捕获命令到内部时钟域 的内部时钟信号和延迟的内部时钟信号

公开(公告)号：US09529379B2

公开(公告)日：2016-12-27

申请号：US14280840

申请日：2014-05-19

Applicant: Micron Technology, Inc.

Inventor： Jongtae Kwak

IPC: G06F1/12 ,  G06F1/04 ,  G11C7/22 ,  H03L7/081 ,  G06F1/10 ,  G06F11/16

CPC classification number: G06F1/04 ,  G06F1/10 ,  G06F1/12 ,  G06F11/1679 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0812

Abstract: An apparatus for synchronizing an output clock signal with an input clock signal includes a first timing synchronization circuit, control logic, and a counter. The first timing synchronization circuit is operable to generate a delay to synchronize a reference clock signal representative of the input clock signal with a feedback clock signal representative of the output clock signal responsive a strobe signal. The control logic is operable to generate an enable signal based on the reference clock signal and generate the strobe signal based on the feedback clock signal. The counter is operable to count cycles of the reference clock signal occurring between the enable signal and the strobe signal to generate a loop count for the first timing synchronization circuit.

Abstract translation: 用于使输出时钟信号与输入时钟信号同步的装置包括第一定时同步电路，控制逻辑和计数器。 第一定时同步电路可操作以产生延迟以使代表输入时钟信号的参考时钟信号与表示响应于选通信号的输出时钟信号的反馈时钟信号同步。 控制逻辑可操作以基于参考时钟信号产生使能信号，并且基于反馈时钟信号产生选通信号。 该计数器可操作地计数在使能信号和选通信号之间出现的参考时钟信号的周期，以产生第一定时同步电路的循环计数。

公开(公告)号：US09508409B2

公开(公告)日：2016-11-29

申请号：US14254378

申请日：2014-04-16

Applicant: Micron Technology, Inc.

Inventor： Mark K. Hadrick ,  Jeffrey P. Wright ,  Victor Wong ,  Simon J. Lovett ,  Donald M. Morgan ,  William F. Jones ,  Sujeet Ayyapureddi ,  Dean D. Gans ,  Jongtae Kwak

IPC: G11C7/22 ,  G11C7/10 ,  G11C8/12

CPC classification number: G11C7/22 ,  G11C7/1009 ,  G11C7/1042 ,  G11C8/12 ,  G11C2207/229

Abstract: Apparatuses and methods for implementing masked write commands are disclosed herein. An example apparatus may include a memory bank, a local buffer circuit, and an address control circuit. The local buffer circuit may be associated with the memory bank. The address control circuit may be coupled to the memory bank and configured to receive a command and an address associated with the command. The address control circuit may include a global buffer circuit configured to store the address. The address control circuit may further be configured to delay the command using one of a plurality of command paths based, at least in part, on a write latency and to provide the address stored in the global buffer circuit to the local buffer circuit to be stored therein.

Abstract translation: 本文公开了用于实现屏蔽写入命令的装置和方法。 示例性装置可以包括存储体，局部缓冲电路和地址控制电路。 本地缓冲电路可以与存储体相关联。 地址控制电路可以耦合到存储体并被配置为接收命令和与该命令相关联的地址。 地址控制电路可以包括被配置为存储地址的全局缓冲电路。 地址控制电路还可以被配置为至少部分地基于写等待时间来延迟使用多个命令路径之一的命令，并且将存储在全局缓冲器电路中的地址提供给要存储的本地缓冲器电路 其中。

公开(公告)号：US09484074B2

公开(公告)日：2016-11-01

申请号：US14258317

申请日：2014-04-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Seong-Hoon Lee ,  Onegyun Na ,  Jongtae Kwak

IPC: G11C7/00 ,  G11C7/02 ,  G11C7/06

CPC classification number: G11C7/065 ,  G11C7/062 ,  G11C2207/063

Abstract: Memories, current mode sense amplifiers, and methods for operating the same are disclosed, including a current mode sense amplifier including cross-coupled p-channel transistors and a load circuit coupled to the cross-coupled p-channel transistors. The load circuit is configured to provide a resistance to control at least in part the loop gain of the current mode sense amplifier, the load circuit including at least passive resistance.

Abstract translation: 公开了一种存储器，电流模式读出放大器及其操作方法，包括一个包括交叉耦合的p沟道晶体管和耦合到交叉耦合的p沟道晶体管的负载电路的电流模式读出放大器。 负载电路被配置为提供至少部分地控制电流模式读出放大器的环路增益的电阻，负载电路至少包括被动电阻。

公开(公告)号：US09373371B2

公开(公告)日：2016-06-21

申请号：US14530911

申请日：2014-11-03

Applicant: Micron Technology, Inc.

Inventor： Jongtae Kwak

IPC: G11C7/10 ,  G11C7/22

CPC classification number: G11C7/106 ,  G11C7/1018 ,  G11C7/1066 ,  G11C7/222

Abstract: A memory, a system and a method for controlling dynamic burst length control data can generate clocks for both an upstream counter and a downstream counter by using substantially the same latency delayed received command indications. A downstream clock generation circuit generates a clock signal from a received command indication delayed by both a delay locked loop and latency delays stored in latency control circuits. An upstream clock generation circuit generates a clock signal from the received command indication delayed by the delay locked loop and capture indications from the latency control circuits.

Abstract translation: 用于控制动态突发长度控制数据的存储器，系统和方法可以通过使用基本上相同的等待时间延迟的接收命令指示来为上游计数器和下游计数器产生时钟。 下行时钟产生电路从延迟锁定环路延迟的接收到的命令指示和等待时间控制电路中存储的等待时延延迟生成时钟信号。 上行时钟发生电路根据延迟锁定环延迟的接收命令指示产生时钟信号，并从等待时间控制电路捕获指示。