公开(公告)号：US20050213384A1

公开(公告)日：2005-09-29

申请号：US11135775

申请日：2005-05-23

申请人： Ji-Young Kim ,  Sang-Yong Kim

发明人： Ji-Young Kim ,  Sang-Yong Kim

IPC分类号： H01L29/78 ,  H01L21/8234 ,  H01L23/31 ,  G11C11/34

CPC分类号： H01L29/6656 ,  H01L21/823437 ,  H01L21/823468 ,  H01L23/3171 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device protecting the ends of a gate line and a method of forming the same are disclosed. The semiconductor device includes a semiconductor substrate, a gate line crossing over the semiconductor substrate, and a protecting pattern covering ends of the gate line. According to the method, a gate line is formed at a semiconductor substrate. A spacer is formed to cover sidewalls of the gate line. A protecting pattern is formed to cover the ends of the gate line. The protecting pattern may be formed of silicon nitride or silicon oxide. Since the protecting pattern protects ends of a gate line, it is possible to prevent gate electrodes from being damaged by a cleaning solution such as SC1 in a subsequent process.

摘要翻译： 公开了保护栅极线的端部的半导体器件及其形成方法。 半导体器件包括半导体衬底，跨越半导体衬底的栅极线和覆盖栅极线的端部的保护图案。 根据该方法，在半导体衬底上形成栅极线。 形成间隔件以覆盖栅极线的侧壁。 形成保护图案以覆盖栅极线的端部。 保护图案可以由氮化硅或氧化硅形成。 由于保护图案保护栅极线的端部，因此可以防止在随后的工艺中栅电极被诸如SC1的清洁溶液损坏。

公开(公告)号：US06903404B2

公开(公告)日：2005-06-07

申请号：US10426153

申请日：2003-04-29

申请人： Ji-Young Kim

发明人： Ji-Young Kim

IPC分类号： H01L23/52 ,  H01L21/3205 ,  H01L21/331 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/10 ,  H01L27/108 ,  H01L29/73

CPC分类号： H01L27/10894 ,  H01L27/0207 ,  H01L27/10808 ,  H01L27/10885 ,  H01L27/10888

摘要： A semiconductor memory device includes a plurality of bit line structures arranged in parallel on a semiconductor substrate and having a plurality of bit lines and an insulating material surrounding the bit lines, an isolation layer formed in a portion in spaces between the bit line structures to define a predetermined active region and having substantially the same height as the bit line structures, a semiconductor layer formed in the predetermined active region surrounded by the bit line structures and the isolation layer and having substantially the same height as the bit line structures and the isolation layer, a plurality of word line structures arranged in parallel on the bit line structures, the isolation layer, and the semiconductor layer, and comprising a plurality of word lines and an insulating material surrounding the word lines, and source and drain regions formed in the semiconductor layer on either side of the word line structures.

摘要翻译： 半导体存储器件包括多个位线结构并行布置在半导体衬底上并且具有多个位线和围绕位线的绝缘材料，隔离层形成在位线结构之间的空间部分中以限定 预定的有源区并且具有与位线结构基本相同的高度;形成在由位线结构和隔离层围绕的预定有源区中并且具有与位线结构和隔离层基本相同的高度的半导体层 ，在位线结构，隔离层和半导体层上平行布置的多个字线结构，并且包括多个字线和围绕字线的绝缘材料，以及形成在半导体中的源极和漏极区域 在字线结构的任一侧的层。

公开(公告)号：US20050098850A1

公开(公告)日：2005-05-12

申请号：US11009913

申请日：2004-12-10

申请人： Ji-Young Kim ,  Je-Min Park

发明人： Ji-Young Kim ,  Je-Min Park

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/60 ,  H01L21/76 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8247 ,  H01L27/08 ,  H01L27/088 ,  H01L27/115 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L29/00

CPC分类号： H01L21/76897 ,  H01L21/76229 ,  H01L21/823481

摘要： A plurality of trenches for defining active regions are formed in a semiconductor substrate, using a plurality of trench masks. A gap fill insulating layer is formed on the resulting structure to fill a gap region bounded by the trench and the trench masks. Next, the trench mask and the gap fill insulating layer are patterned to form a trench mask pattern and a gap fill insulating pattern for defining a slit-type opening, extending across and exposes the active region. A gate pattern is formed in the slit-type opening and the trench mask pattern is removed to form a contact opening exposing the active region. Next, a contact plug is formed to fill the contact opening. Here, the contact opening is self-alignedly formed using an etch selectivity between the trench mask and the gap fill insulating layer. The resulting contact opening is a vacancy in a rectangular parallelepiped shape.

摘要翻译： 使用多个沟槽掩模在半导体衬底中形成用于限定有源区的多个沟槽。 在所得结构上形成间隙填充绝缘层，以填充由沟槽和沟槽掩模界定的间隙区域。 接下来，将沟槽掩模和间隙填充绝缘层图案化以形成沟槽掩模图案和间隙填充绝缘图案，用于限定狭缝型开口，延伸跨过并暴露活性区域。 在狭缝型开口中形成栅极图案，并且去除沟槽掩模图案以形成暴露有源区的接触开口。 接下来，形成接触插塞以填充接触开口。 这里，使用沟槽掩模和间隙填充绝缘层之间的蚀刻选择性，自对准地形成接触开口。 所形成的接触开口是长方体形状的空位。

公开(公告)号：US06710726B2

公开(公告)日：2004-03-23

申请号：US10317327

申请日：2002-12-12

申请人： Ji-Young Kim ,  Jae-yup Lee

发明人： Ji-Young Kim ,  Jae-yup Lee

IPC分类号： H03M900

CPC分类号： H03M9/00

摘要： A serializer-deserializer circuit having increased margins for setup and hold time is provided. The serializer-deserializer circuit comprises a data skew control circuit, a latch circuit, a serial converter circuit, and a phase locked loop (PLL). The data skew control circuit receives a first clock signal and a data signal, delays the data signal, and outputs a delayed data signal in response to a reference clock signal. The latch circuit latches and outputs the delayed data signal in response to the reference clock signal. The serial converter circuit receives and serializes an output signal of the latch circuit in response to the reference clock signal to output serial data. The PLL generates the reference clock signal in response to an external reference clock signal. Instead of using the first clock signal input with the data signal, the serializer-deserializer circuit uses a signal, which is generated by an oscillator and thus has a small amount of jitter, as an input clock to the PLL so that a reference clock signal without noise is generated to improve the operation of the serializer-deserializer circuit. In addition, the reference clock signal output from the PLL is locked to the data signal to increase margins for setup and hold time during the latch operation of the data signal.

摘要翻译： 提供了一种具有增加的建立和保持时间余量的串行器 - 解串器电路。 串行器 - 解串器电路包括数据偏移控制电路，锁存电路，串行转换器电路和锁相环（PLL）。 数据偏移控制电路接收第一时钟信号和数据信号，延迟数据信号，并响应于参考时钟信号输出延迟的数据信号。 锁存电路根据参考时钟信号锁存和输出延迟的数据信号。 串行转换器电路响应于参考时钟信号接收和串行锁存电路的输出信号以输出串行数据。 PLL根据外部参考时钟信号产生参考时钟信号。 串行器 - 解串器电路不是使用与数据信号一起输入的第一时钟信号，而是使用由振荡器产生的信号，因此具有少量的抖动作为PLL的输入时钟，使得参考时钟信号 不产生噪声，从而改善了串串器 - 解串器电路的运行。 此外，从PLL输出的参考时钟信号被锁定到数据信号，以在数据信号的锁存操作期间增加用于建立和保持时间的裕度。

公开(公告)号：US06682721B2

公开(公告)日：2004-01-27

申请号：US10049817

申请日：2002-02-19

申请人： Ji-Young Kim ,  Jong-Ho Kim ,  Sug-Youn Chang ,  Sei-Young Yun

发明人： Ji-Young Kim ,  Jong-Ho Kim ,  Sug-Youn Chang ,  Sei-Young Yun

IPC分类号： A61K720

CPC分类号： A61Q11/00 ,  A61K8/0208 ,  A61K8/22 ,  A61K8/24 ,  A61K8/8164 ,  A61K8/817 ,  A61K8/8176 ,  A61K8/8182

摘要： The present invention relates to a dry type tooth whitening patch comprising peroxide as a tooth whitening agent. In particular, disclosed is a dry type tooth whitening patch in which a peroxide is contained, as a teeth whitening agent, in a matrix type adhesive layer. The adhesive layer includes, as a base polymer thereof, a hydrophilic glass polymer which provides a strong adhesion to teeth while releasing the tooth whitening agent when hydrated on the enamel layers of teeth in the moist oral cavity. The dry type patch according to the present invention is convenient in use, as compared to wet type patches. Further, it exhibits a superior adhesion while being maintained in a state attached to the teeth for a lengthened period of time so as to assure an enough contact time between the whitening agent in the patch and stains on the teeth, thereby giving a sufficient whitening effect.

公开(公告)号：US10681196B2

公开(公告)日：2020-06-09

申请号：US12753414

申请日：2010-04-02

申请人： Hye-Soo Lee ,  Ji-Young Kim ,  Seong-Hoon Kang ,  Sun-Haeng Jo

发明人： Hye-Soo Lee ,  Ji-Young Kim ,  Seong-Hoon Kang ,  Sun-Haeng Jo

IPC分类号： G06F3/0481 ,  H04M1/2745 ,  G06Q30/02 ,  H04M1/725

摘要： Provided are a mobile terminal and method for providing a human network management service in the mobile terminal, the method including receiving human network data from a social network service site; checking and converting a schema of each received human network data into a predetermined schema; and updating human network data in the mobile terminal according to the converted schema.

公开(公告)号：US08884340B2

公开(公告)日：2014-11-11

申请号：US13298644

申请日：2011-11-17

申请人： Ji-Young Kim ,  Gyo-Young Jin ,  Hyeong-Sun Hong ,  Yong-Chul Oh ,  Yoo-Sang Hwang ,  Sung-Kwan Choi ,  Dong-Soo Woo ,  Hyun-Woo Chung

发明人： Ji-Young Kim ,  Gyo-Young Jin ,  Hyeong-Sun Hong ,  Yong-Chul Oh ,  Yoo-Sang Hwang ,  Sung-Kwan Choi ,  Dong-Soo Woo ,  Hyun-Woo Chung

IPC分类号： H01L21/336 ,  H01L29/772 ,  G11C11/404 ,  H01L27/108 ,  H01L29/66 ,  H01L29/78 ,  G11C11/408 ,  H01L29/417 ,  H01L29/423 ,  H01L21/8234

CPC分类号： G11C11/4096 ,  G11C11/404 ,  G11C11/4085 ,  H01L21/823437 ,  H01L27/10823 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10891 ,  H01L27/10894 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/66484 ,  H01L29/66613 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7831

摘要： A semiconductor device may include a semiconductor substrate with first and second spaced apart source/drain regions defining a channel region therebetween and a control gate structure on the channel region between the first and second spaced apart source/drain regions. More particularly, the control gate structure may include a first gate electrode on the channel region adjacent the first source/drain region, and a second gate electrode on the channel region adjacent the second source/drain region. Moreover, the first and second gate electrodes may be electrically isolated. Related devices, structures, methods of operation, and methods of fabrication are also discussed.

摘要翻译： 半导体器件可以包括具有限定其间的沟道区的第一和第二间隔开的源极/漏极区的半导体衬底，以及在第一和第二间隔开的源极/漏极区之间的沟道区上的控制栅极结构。 更具体地，控制栅极结构可以包括在与第一源极/漏极区域相邻的沟道区域上的第一栅极电极以及与第二源极/漏极区域相邻的沟道区域上的第二栅极电极。 此外，第一和第二栅电极可以是电隔离的。 还讨论了相关设备，结构，操作方法和制造方法。

公开(公告)号：US08835910B2

公开(公告)日：2014-09-16

申请号：US13171184

申请日：2011-06-28

申请人： Ji-Young Kim ,  Mu-Hyun Kim ,  Jin-Goo Kang ,  Dong-Kyu Lee ,  Jae-Bok Kim

发明人： Ji-Young Kim ,  Mu-Hyun Kim ,  Jin-Goo Kang ,  Dong-Kyu Lee ,  Jae-Bok Kim

IPC分类号： H01L29/08 ,  H01L27/32

CPC分类号： H01L27/3258 ,  H01L27/3246

摘要： An organic light emitting display apparatus in which image quality can be improved. The organic light emitting display apparatus includes: a substrate; a first electrode disposed on the substrate; a pixel definition layer formed on the first electrode and having an opening portion through which a region of the first electrode is exposed; an intermediate layer connected to the first electrode through the opening portion and including an organic emission layer; a second electrode electrically connected to the intermediate layer; and an inorganic planarization pattern portion disposed between the substrate and the first electrode and formed to at least correspond to the opening portion.

摘要翻译： 一种能够提高图像质量的有机发光显示装置。 有机发光显示装置包括：基板; 设置在所述基板上的第一电极; 形成在第一电极上并具有开口部分的像素限定层，第一电极的区域通过该开口部分露出; 中间层，其通过所述开口部分连接到所述第一电极并且包括有机发射层; 电连接到所述中间层的第二电极; 以及设置在所述基板和所述第一电极之间并且至少形成为至少对应于所述开口部分的无机平坦化图案部分。

公开(公告)号：US08585391B2

公开(公告)日：2013-11-19

申请号：US13238805

申请日：2011-09-21

申请人： Jin-Ho Kim ,  Yo-Han Ahn ,  Jeong-In Yoon ,  Ji-Young Kim

发明人： Jin-Ho Kim ,  Yo-Han Ahn ,  Jeong-In Yoon ,  Ji-Young Kim

IPC分类号： G03F1/82 ,  G03F1/62

CPC分类号： G03F1/64 ,  B08B7/0042 ,  B23K26/0006 ,  B23K26/032 ,  B23K26/0622 ,  B23K26/142 ,  B23K26/352 ,  B23K26/361 ,  B23K2103/56 ,  G03F1/82

摘要： A photomask cleaning apparatus includes a photomask receiving stage and a laser supply unit. The photomask receiving stage is configured to receive and retain a photomask in a desired orientation. The photomask has a front face having a pellicle adhesive residue region thereon. The desired orientation is with the front face positioned to allow gravity to move particles on the front face away from the front face without interference from the front face of the photomask. The laser supply unit is configured to generate a laser beam that irradiates a target region on the front face of the photomask to remove a pellicle adhesive residue from the target region. The photomask cleaning apparatus is configured to move the target region on the front face of the photomask to irradiate the entire pellicle adhesive residue region. Methods of using the photomask cleaning apparatus are also provided.

摘要翻译： 光掩模清洁装置包括光掩模接收台和激光供给单元。 光掩模接收台被配置为以期望的方向接收和保持光掩模。 光掩模具有在其上具有防护薄膜粘合剂残留区域的前表面。 期望的取向是将前表面定位成允许重力将前表面上的颗粒移动远离前表面，而不会受到光掩模前表面的干扰。 激光供给单元被配置为产生照射光掩模的前表面上的目标区域以从目标区域去除防护薄膜组合物残留物的激光束。 光掩模清洁装置被配置为移动光掩模的前表面上的目标区域以照射整个防粘膜残留区域。 还提供了使用光掩模清洁装置的方法。

公开(公告)号：US20130015429A1

公开(公告)日：2013-01-17

申请号：US13180601

申请日：2011-07-12

申请人： Augustin J. Hong ,  Ji-Young Kim ,  Kang-Lung Wang

发明人： Augustin J. Hong ,  Ji-Young Kim ,  Kang-Lung Wang

IPC分类号： H01L29/12

CPC分类号： B82Y10/00 ,  G11C16/04 ,  G11C2213/35 ,  H01L27/11529 ,  H01L27/11551 ,  H01L29/1606 ,  H01L29/42324 ,  H01L29/7881

摘要： A Graphene Flash Memory (GFM) device is disclosed. In general, the GFM device includes a number of memory cells, where each memory cell includes a graphene channel, a graphene storage layer, and a graphene electrode. In one embodiment, by using a graphene channel, graphene storage layer, and graphene electrode, the memory cells of the GFM device are enabled to be scaled down much more than memory cells of a conventional flash memory device. More specifically, in one embodiment, the GFM device has a feature size less than 25 nanometers, less than or equal to 20 nanometers, less than or equal to 15 nanometers, less than or equal to 10 nanometers, or less than or equal to 5 nanometers.

摘要翻译： 公开了一种石墨烯闪存（GFM）装置。 通常，GFM器件包括多个存储器单元，其中每个存储器单元包括石墨烯通道，石墨烯存储层和石墨烯电极。 在一个实施例中，通过使用石墨烯通道，石墨烯存储层和石墨烯电极，能够使GFM器件的存储器单元比常规闪存器件的存储器单元小得多。 更具体地说，在一个实施例中，GFM器件具有小于25纳米，小于或等于20纳米，小于或等于15纳米，小于或等于10纳米，或小于或等于5纳米 纳米。