公开(公告)号：US08415783B1

公开(公告)日：2013-04-09

申请号：US11973245

申请日：2007-10-04

申请人： Arifur Rahman ,  Raghunandan Chaware

发明人： Arifur Rahman ,  Raghunandan Chaware

IPC分类号： H01L23/02 ,  H01L23/34

CPC分类号： H01L23/3107 ,  G01R31/2884 ,  H01L21/561 ,  H01L22/32 ,  H01L23/3135 ,  H01L23/36 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/15172 ,  H01L2924/15311 ,  H01L2924/00

摘要： A packaged integrated circuit (“IC”) has a daughter IC die stacked on a backside of a parent IC die. Backside fill material is applied to the backside of the parent IC die to provide a planarized surface.

摘要翻译： 封装集成电路（IC）具有堆叠在母IC芯片的背面的子IC芯片。 将背面填充材料施加到母IC芯片的背面以提供平坦化表面。

公开(公告)号：US08082537B1

公开(公告)日：2011-12-20

申请号：US12361115

申请日：2009-01-28

申请人： Arifur Rahman

发明人： Arifur Rahman

IPC分类号： G06F17/50 ,  H01L29/06 ,  H01L29/40

CPC分类号： G06F17/5054 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/13027 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2224/05552 ,  H01L2924/00

摘要： Examples of the invention relate to a method, apparatus, and computer readable medium for designing a mother integrated circuit (IC) configured for stacking with at least one daughter IC. A layout of the mother IC includes at least one interface tile having an electrical configuration for communicating with interface logic of the daughter IC. The method includes: obtaining design rules for through die vias (TDVs) to be formed in the mother IC for implementing connections between the at least one interface tile and a physical interface of the daughter IC; defining a layout of the TDVs in the mother IC according to the design rules; and defining at least one mask for programming interconnect on the mother IC to physically connect the TDVs between the at least one interface tile and the physical interface of the daughter IC without changing the electrical configuration of the at least one interface tile.

摘要翻译： 本发明的实例涉及用于设计配置为与至少一个子IC堆叠的母集成电路（IC）的方法，装置和计算机可读介质。 母IC的布局包括至少一个接口瓦片，其具有用于与子IC的接口逻辑通信的电气配置。 该方法包括：获得要在母IC中形成的通孔（TDV）的设计规则，用于实现至少一个接口片和子IC的物理接口之间的连接; 根据设计规则定义母IC中的TDV布局; 以及定义用于在所述母IC上编程互连的至少一个掩模，以物理地连接所述至少一个接口瓦片和所述子IC的物理接口之间的TDV，而不改变所述至少一个接口瓦片的电气配置。

公开(公告)号：US08058707B1

公开(公告)日：2011-11-15

申请号：US12041610

申请日：2008-03-03

申请人： Stephen M. Trimberger ,  Arifur Rahman

发明人： Stephen M. Trimberger ,  Arifur Rahman

IPC分类号： H01L21/44 ,  H01L23/48 ,  H01L29/41

CPC分类号： H01L23/528 ,  H01L23/481 ,  H01L25/0652 ,  H01L2224/16225 ,  H01L2924/15311

摘要： Semiconductor devices having redundant through-die vias (TDVs) and methods of fabricating the same are described. A substrate is provided having conductive interconnect formed on an active side thereof. Through die vias (TDVs) are formed in the substrate between a backside and the active side thereof. The TDVs include signal TDVs, redundant TDVs (i.e., redundant signal TDVs), and power supply TDVs. The signal TDVs are spaced apart from the redundant TDVs to form a pattern of TDV pairs. The power supply TDVs are interspersed among the TDV pairs. The conductive interconnect includes first signal conductors electrically coupling each of the signal TDVs to a respective one of the redundant TDVs defining a respective one of the TDV pairs.

摘要翻译： 描述了具有冗余通孔（TDV）的半导体器件及其制造方法。 提供了在其活性侧形成有导电互连的衬底。 通过裸片（TDV）形成在基板的背侧和其活动侧之间。 TDV包括信号TDV，冗余TDV（即，冗余信号TDV）和电源TDV。 信号TDV与冗余TDV间隔开以形成TDV对的模式。 电源TDV分散在TDV对之间。 导电互连包括将每个信号TDV电耦合到限定TDV对中的相应一个的冗余TDV中的相应一个的第一信号导体。

公开(公告)号：US07998853B1

公开(公告)日：2011-08-16

申请号：US12419276

申请日：2009-04-06

申请人： Arifur Rahman

发明人： Arifur Rahman

IPC分类号： H01L21/4743

CPC分类号： H01L21/76898 ,  H01L22/14 ,  H01L22/20 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06596 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/81

摘要： Methods for making and testing a semiconductor device with through substrate vias are described. In some examples, a method of making a semiconductor device includes: forming through substrate vias (TSVs) in a substrate having an integrated circuit (IC) die, the substrate including an active side and a backside, the active side having conductive interconnect formed thereon, the TSVs including exposed portions on the backside of the substrate; patterning first metal on the active side of the substrate to electrically couple the TSVs to a portion of the conductive interconnect; and coupling the exposed portions of the TSVs on the backside of the substrate to electrically couple together the plurality of TSVs.

摘要翻译： 描述了通过衬底通孔制造和测试半导体器件的方法。 在一些示例中，制造半导体器件的方法包括：在具有集成电路（IC）裸片的衬底中形成通过衬底通孔（TSV），所述衬底包括有源侧和背面，所述有源侧在其上形成导电互连 ，TSV包括在衬底的背面上的暴露部分; 在衬底的有源侧上构图第一金属以将TSV电耦合到导电互连的一部分; 并且将衬底的背面上的TSV的暴露部分耦合在一起以将多个TSV电耦合在一起。

公开(公告)号：US07989959B1

公开(公告)日：2011-08-02

申请号：US12361827

申请日：2009-01-29

申请人： Arifur Rahman

发明人： Arifur Rahman

IPC分类号： H01L23/42 ,  H01L21/44

CPC分类号： H01L23/3128 ,  H01L21/563 ,  H01L23/481 ,  H01L24/06 ,  H01L24/14 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05554 ,  H01L2224/0557 ,  H01L2224/0603 ,  H01L2224/06132 ,  H01L2224/06519 ,  H01L2224/14132 ,  H01L2224/14135 ,  H01L2224/14136 ,  H01L2224/14177 ,  H01L2224/14515 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2224/05552 ,  H01L2924/00

摘要： A stacked-die integrated circuit and a method of fabricating same. The stacked-die integrated circuit has circuitry formed in the first surface of a mother die, a plurality of through-die vias with at least one through-die via providing electrical connection between the circuitry of the mother die and the second surface and a plurality of contact pads formed in the second surface of the semiconductor die for mounting a daughter die wherein some of the contact pads are electrically isolated dummy pads.

摘要翻译： 堆叠管芯集成电路及其制造方法。 堆叠管芯集成电路具有形成在母模的第一表面中的电路，具有至少一个通孔的多个通孔通孔，其通过在母模的电路和第二表面之间提供电连接，以及多个 形成在半导体管芯的第二表面中的用于安装子管芯的接触焊盘，其中一些接触焊盘是电隔离的假焊盘。

公开(公告)号：US20110012633A1

公开(公告)日：2011-01-20

申请号：US12505215

申请日：2009-07-17

申请人： Arifur Rahman ,  Hong-Tsz Pan ,  Bang-Thu Nguyen

发明人： Arifur Rahman ,  Hong-Tsz Pan ,  Bang-Thu Nguyen

IPC分类号： G01R31/02

CPC分类号： G01R31/318544 ,  H01L2224/16145

摘要： An integrated circuit device is described that includes a stacked die and a base die having probe pads that directly couple to test logic of the base die so as to implement a scan chain for testing of the integrated circuit device. The base die further includes contacts disposed on a back side of the base die and through-die vias coupled to the contacts and coupled to programmable logic of the base die. In addition, the base die includes a first probe pad configured to couple test input, a second probe pad configured to couple test output and a third probe pad configured to couple control signals. Test logic of the base die is configured to couple to additional test logic of the stacked die so as to implement a scan chain for testing of the integrated circuit device. In accordance with aspects of the present invention, the first probe pad, the second probe pad and the third probe pad are coupled directly to the test logic such that configuration of the programmable logic is not required for coupling the test input, the test output and the control signal between the base die and the stacked die so as to implement the scan chain.

摘要翻译： 描述了一种集成电路器件，其包括具有探针焊盘的堆叠管芯和基座管芯，所述探针焊盘直接耦合到所述基座管芯的测试逻辑，以便实现用于所述集成电路器件的测试的扫描链。 基模还包括设置在基模的背面上的触点和耦合到触点并连接到基模的可编程逻辑的通孔通孔。 此外，基座芯片包括被配置为耦合测试输入的第一探针焊盘，被配置为耦合测试输出的第二探针焊盘和被配置为耦合控制信号的第三探针焊盘。 基模的测试逻辑被配置为耦合到堆叠管芯的附加测试逻辑，以便实现用于集成电路器件测试的扫描链。 根据本发明的方面，第一探针焊盘，第二探针焊盘和第三探针焊盘直接耦合到测试逻辑，使得不需要可编程逻辑的配置来耦合测试输入，测试输出和 基模和堆叠管芯之间的控制信号，以实现扫描链。

公开(公告)号：US07863092B1

公开(公告)日：2011-01-04

申请号：US12242492

申请日：2008-09-30

申请人： Raghunandan Chaware ,  Arifur Rahman

发明人： Raghunandan Chaware ,  Arifur Rahman

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L23/3114 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/11 ,  H01L24/16 ,  H01L24/31 ,  H01L24/81 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/16235 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/18161 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2224/05552

摘要： Disclosed is a method of fabricating an integrated circuit assembly in which a plurality of mother dice having a plurality of through-die vias (TDVs) are formed in the first (active) surface of a semiconductor wafer, a substrate is attached to the active surface of the wafer, the second (inactive) surface is back-ground to expose one end of the through-die vias, a plurality of daughter dice are mounted to the inactive surface of the wafer, each daughter die being electrically coupled to a mother die, and the mother dice are then singulated. Attaching the substrate can be accomplished by adhering a glass wafer carrier to the wafer. The wafer carrier allows handling of the wafer during back-grinding the inactive surface, forming under-bump metal (UBM) pads on the TDVs and attaching the daughter dice.

摘要翻译： 公开了一种制造集成电路组件的方法，其中在半导体晶片的第一（有源）表面中形成多个具有多个通孔（TDV）的母模，衬底附着到有源表面 ，第二（非活动）表面被背面暴露以暴露通孔的一端，多个子模具被安装到晶片的非活性表面，每个子模具电耦合到母模 然后将母体骰子分开。 可以通过将玻璃晶片载体粘附到晶片来实现安装基板。 晶片载体允许在对非活性表面进行后研磨期间处理晶片，在TDV上形成凸块下金属（UBM）焊盘并附接子芯。

公开(公告)号：US07727896B1

公开(公告)日：2010-06-01

申请号：US12266194

申请日：2008-11-06

申请人： Arifur Rahman

发明人： Arifur Rahman

IPC分类号： H01L21/311

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/157 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A method for forming a stacked-die structure is disclosed in which a buried oxide layer is formed in a semiconductor wafer. Device layers and metal layers are formed on the face side of the semiconductor wafer, defining dice, with each die including an interconnect region. Openings are etched in the interconnect regions that extend through the semiconductor wafer so as to expose portions of the buried oxide layer. Conductive material is deposited within the openings so as to form through-die vias. The semiconductor wafer is then attached to a wafer support structure and material is removed from the backside of the semiconductor wafer so as to form an oxide layer having a thickness that is less than the initial thickness of the buried oxide layer. Openings are then etched within the backside of the semiconductor wafer so as to expose the through-die vias, micro-bumps are deposited over the through-die vias, and stacked dice are attached to the micro-bumps so as to electrically couple the stacked dice to the through-die vias. Thereby, a stacked die structure is formed that includes an oxide layer on the backside of the base die. Since the method does not include any high temperature process steps after the semiconductor wafer has been attached to the wafer support structure, thermally-released double-sided tape or adhesive having a low thermal budget can be used to attach the semiconductor wafer to the wafer support structure.

摘要翻译： 公开了一种用于形成堆叠管芯结构的方法，其中在半导体晶片中形成掩埋氧化物层。 器件层和金属层形成在半导体晶片的正面上，限定晶片，每个管芯包括互连区域。 在穿过半导体晶片的互连区域中蚀刻开口，以露出掩埋氧化物层的部分。 导电材料沉积在开口内以便形成通孔。 然后将半导体晶片附接到晶片支撑结构，并且从半导体晶片的背面去除材料，以便形成厚度小于掩埋氧化物层的初始厚度的氧化物层。 然后在半导体晶片的背面蚀刻开口，以便露出通孔通孔，微凸块沉积在通孔通孔之上，并且堆叠的管芯附着到微突起，以电耦合堆叠 骰子穿过通孔。 由此，形成在基模的背面具有氧化物层的堆叠的模具结构。 由于该方法在半导体晶片已经附着到晶片支撑结构之后不包括任何高温工艺步骤，所以可以使用具有低热预算的热释放双面胶带或粘合剂将半导体晶片附着到晶片支撑件 结构体。

公开(公告)号：US07701251B1

公开(公告)日：2010-04-20

申请号：US12043843

申请日：2008-03-06

申请人： Arifur Rahman ,  Chidamber R. Kulkarni

发明人： Arifur Rahman ,  Chidamber R. Kulkarni

IPC分类号： H03K19/177 ,  H01L25/00

CPC分类号： H01L25/18 ,  H01L25/0657 ,  H01L2224/0554 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： Methods and apparatus for implementing a stacked memory-programmable integrated circuit system-in-package are described. An aspect of the invention relates to a semiconductor device. A first integrated circuit (IC) die is provided having an array of tiles that form a programmable fabric of a programmable integrated circuit. A second IC die is stacked on the first IC die and connected therewith via inter-die connections. The second IC die includes banks of memory coupled to input/output (IO) data pins. The inter-die connections couple the IO data pins to the programmable fabric such that all of the banks of memory are accessible in parallel.

摘要翻译： 描述了用于实现堆叠式存储器可编程集成电路系统级封装的方法和装置。 本发明的一个方面涉及一种半导体器件。 提供了具有形成可编程集成电路的可编程结构的瓦片阵列的第一集成电路（IC）裸片。 第二IC芯片堆叠在第一IC裸片上并通过晶片间连接与之连接。 第二个IC芯片包括耦合到输入/输出（IO）数据引脚的存储器组。 管芯间连接将IO数据引脚耦合到可编程结构，使得所有存储器组可并行访问。

公开(公告)号：US07545177B1

公开(公告)日：2009-06-09

申请号：US11725742

申请日：2007-03-20

申请人： Sean W. Kao ,  Tim Tuan ,  Arifur Rahman

发明人： Sean W. Kao ,  Tim Tuan ,  Arifur Rahman

IPC分类号： H03K19/096

CPC分类号： H03K19/0016

摘要： Leakage current reduction from a logic block is implemented via power gating transistors that exhibit increased gate oxide thickness as compared to the thin-oxide devices of the power gated logic block. Increased gate oxide further allows increased gate to source voltage differences to exist on the power gating devices, which enhances performance and reduces gate leakage even further. Placement of the power gating transistors in proximity to other increased gate oxide devices minimizes area penalties caused by physical design constraints of the semiconductor die.

摘要翻译： 与电源门控逻辑块的薄氧化物器件相比，通过电源门控晶体管实现了从逻辑块的漏电流减小，其表现出增加的栅极氧化物厚度。 增加的栅极氧化物进一步允许在电源门控器件上存在增加的栅极 - 源极电压差，这进一步提高了性能并降低了栅极泄漏。 功率门控晶体管靠近其他增加的栅极氧化物器件的放置最小化由半导体管芯的物理设计约束引起的面积损失。