公开(公告)号：US09030863B2

公开(公告)日：2015-05-12

申请号：US14038434

申请日：2013-09-26

Applicant: QUALCOMM Incorporated

Inventor： Chirag Gulati ,  Rakesh Kumar Sinha ,  Ritu Chaba ,  Sei Seung Yoon

IPC: G11C11/00 ,  G11C11/419 ,  H01L27/11

CPC classification number: G11C11/419 ,  G11C8/08 ,  G11C8/14 ,  H01L27/1104 ,  H01L27/1116

Abstract: An integrated circuit includes one or more bit cells, a word line coupled to the one or more bit cells, and a dummy word line arranged with the word line to have a capacitance therebetween. The capacitance provides a voltage boost or reduction of the word line to assist read and write operations.

Abstract translation: 集成电路包括一个或多个位单元，耦合到所述一个或多个位单元的字线以及与所述字线布置以在其间具有电容的虚拟字线。 该电容提供了字线的升压或降压以辅助读和写操作。

公开(公告)号：US20140185349A1

公开(公告)日：2014-07-03

申请号：US13730524

申请日：2012-12-28

Applicant: QUALCOMM INCORPORATED

Inventor： Esin Terzioglu ,  Nishith Desai ,  Rakesh Vattikonda ,  ChangHo Jung ,  Sei Seung Yoon

IPC: G11C15/04

CPC classification number: G11C15/04 ,  G11C15/00 ,  G11C15/043 ,  G11C15/046

Abstract: A static, ternary content addressable memory (TCAM) includes a key cell and a mask cell coupled to intermediate match lines. The key cell is coupled to a first pull-down transistor and a first pull-up transistor. The mask cell is coupled to a second pull-down transistor and a second pull-up transistor. The first pull-down transistor and second pull-down transistor are connected in parallel and the first pull-up transistor and second pull-up transistor are connected in series. A match line output is also coupled to the first pull-down transistor and second pull-down transistor and further coupled to the first pull-up transistor and second pull-up transistor.

Abstract translation: 静态三元内容可寻址存储器（TCAM）包括密钥单元和耦合到中间匹配行的掩码单元。 关键单元耦合到第一下拉晶体管和第一上拉晶体管。 掩模单元耦合到第二下拉晶体管和第二上拉晶体管。 第一下拉晶体管和第二下拉晶体管并联连接，第一上拉晶体管和第二上拉晶体管串联连接。 匹配线输出还耦合到第一下拉晶体管和第二下拉晶体管，并且还耦合到第一上拉晶体管和第二上拉晶体管。

公开(公告)号：US20140112061A1

公开(公告)日：2014-04-24

申请号：US13656593

申请日：2012-10-19

Applicant: QUALCOMM INCORPORATED

Inventor： Changho Jung ,  Nishith Desai ,  Sei Seung Yoon

IPC: G11C7/00

CPC classification number: G11C11/418 ,  G11C8/08 ,  G11C11/419

Abstract: A write-assisted memory. The write-assisted memory includes a word-line decoder that is implemented within a low VDD power domain. The write-assisted memory also includes a write-segment controller that is partially implemented within the low VDD power domain and is partially implemented within a high VDD power domain. The write-assisted memory further includes a local write word-line decoder that is implemented within the high VDD power domain.

Abstract translation: 写辅助记忆。 写辅助存储器包括在低VDD功率域内实现的字线解码器。 写辅助存储器还包括写入段控制器，其部分地在低VDD功率域内实现，并且部分地在高VDD功率域内实现。 写辅助存储器还包括在高VDD功率域内实现的本地写字线解码器。

公开(公告)号：US10446196B1

公开(公告)日：2019-10-15

申请号：US16164108

申请日：2018-10-18

Applicant: QUALCOMM Incorporated

Inventor： Mukund Narasimhan ,  Sharad Kumar Gupta ,  Adithya Bhaskaran ,  Sei Seung Yoon

IPC: G11C5/14 ,  G11C11/417

Abstract: A dual-power-domain SRAM is disclosed in which the dual power domains may be powered up or down in whatever order is desired. For example, a (CX) power domain may be powered up first, followed by a memory (MX) power domain. Conversely, the MX power domain may be powered up prior to the CX domain.

公开(公告)号：US20180046209A1

公开(公告)日：2018-02-15

申请号：US15791226

申请日：2017-10-23

Applicant: QUALCOMM Incorporated

Inventor： Sanjay Bhagawan Patil ,  Daniel Stasiak ,  Martin Pierre Saint-Laurent ,  Rui Li ,  Bin Liang ,  Sei Seung Yoon ,  Chulmin Jung

IPC: G05F1/10 ,  G06F1/32 ,  H02M1/32

CPC classification number: G05F1/10 ,  G06F1/26 ,  G06F1/263 ,  G06F1/3287 ,  G06F1/329 ,  H02M1/32

Abstract: A computer-readable storage medium for controlling voltage droop storing instructions that, when executed by a processor, cause a device to perform operations including receiving a first voltage to a first input of a first component of a device. The first voltage corresponding to a first logical value causes a first internal power supply of the first component to be charged using an external power supply. The operations further include providing a second voltage to a second input of a second component of the device in response to a first voltage level of the first internal power supply satisfying a second voltage level. The second voltage corresponding to the first logical value causes a second internal power supply of the second component of the device to be charged using the external power supply.

公开(公告)号：US20170300251A1

公开(公告)日：2017-10-19

申请号：US15132026

申请日：2016-04-18

Applicant: QUALCOMM Incorporated

Inventor： Anil Kota ,  Sei Seung Yoon ,  Bhadri Kubendran

IPC: G06F3/06 ,  G06F11/10 ,  G06F11/263

CPC classification number: G06F3/0619 ,  G06F3/065 ,  G06F3/0679 ,  G06F11/108 ,  G06F11/2635 ,  G06F21/78 ,  G11C17/146

Abstract: A method includes: reading a plurality of words from a one-time program (OTP) memory of a processing chip, wherein each of the words includes secure data for the chip and bits corresponding to a check pattern; comparing the bits corresponding to the check pattern to a preprogrammed check pattern; detecting an error based on comparing the bits corresponding to the check pattern to the preprogrammed check pattern; and performing an action by the processing chip in response to detecting the error.

公开(公告)号：US09536578B2

公开(公告)日：2017-01-03

申请号：US13863989

申请日：2013-04-16

Applicant: QUALCOMM Incorporated

Inventor： Chulmin Jung ,  Changho Jung ,  Sei Seung Yoon ,  Rakesh Vattikonda ,  Nishith Desai

IPC: G11C7/12 ,  G11C7/10 ,  G11C11/419

CPC classification number: G11C7/12 ,  G11C7/1084 ,  G11C7/1096 ,  G11C11/419

Abstract: A write driver for a memory circuit includes a control circuit configured to: operate a first push-pull driver to generate a first drive signal in a first voltage domain at a first node based on an input signal in a second domain and in response to a mode select signal being in a first mode, wherein the first drive signal is at a same logic level as the input signal; operate a second push-pull driver to generate a second drive signal in the first voltage domain at a second node based on the input signal and in response to the mode select signal being in the first mode, wherein the second drive signal is at a complement logic level with respect to the input signal; and operate the first and second push-pull drivers to float the first and second nodes in response to the mode select signal being in a second mode.

Abstract translation: 用于存储器电路的写驱动器包括控制电路，该控制电路被配置为：基于第二域中的输入信号，并响应于第一推挽驱动器响应于第一推挽驱动器，在第一节点处的第一电压域中产生第一驱动信号 模式选择信号处于第一模式，其中第一驱动信号处于与输入信号相同的逻辑电平; 操作第二推挽驱动器以基于输入信号在第二节点处的第一电压域中产生第二驱动信号，并且响应于模式选择信号处于第一模式，其中第二驱动信号为补码 相对于输入信号的逻辑电平; 并且响应于所述模式选择信号处于第二模式，操作所述第一和第二推挽驱动器使所述第一和第二节点浮动。

公开(公告)号：US09484110B2

公开(公告)日：2016-11-01

申请号：US13953511

申请日：2013-07-29

Applicant: QUALCOMM Incorporated

Inventor： Sei Seung Yoon ,  Chulmin Jung ,  Esin Terzioglu ,  Steven Mark Millendorf

IPC: G11C17/12 ,  G11C7/24

CPC classification number: G11C17/12 ,  G11C7/24

Abstract: A mask-programmed read-only memory (MROM) has a plurality of column line pairs, each having a bit line and a complement bit line. The MROM includes a plurality of memory cells corresponding to a plurality of intersections between the column line pairs and a plurality of word lines. Each memory cell includes a high Vt transistor and a low Vt transistor.

Abstract translation: 掩模编程的只读存储器（MROM）具有多个列线对，每一列具有位线和补码位线。 MROM包括与列线对和多个字线之间的多个交点相对应的多个存储单元。 每个存储单元包括高Vt晶体管和低Vt晶体管。

公开(公告)号：US09324416B2

公开(公告)日：2016-04-26

申请号：US14464627

申请日：2014-08-20

Applicant: QUALCOMM Incorporated

Inventor： Sei Seung Yoon ,  Tony Chung Yiu Kwok ,  Changho Jung ,  Nishith Nitin Desai

IPC: G11C16/04 ,  G11C11/419 ,  G11C7/10 ,  G11C7/22

CPC classification number: G11C11/419 ,  G11C7/106 ,  G11C7/1072 ,  G11C7/1075 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222 ,  G11C8/16 ,  G11C11/412

Abstract: A memory and a method for operating the memory provided. In one aspect, the memory may be a PDP memory. The memory includes a control circuit configured to generate a first clock and a second clock in response an edge of a clock for an access cycle. A first input circuit is configured to receive an input for a first memory access based on the first clock. The first input circuit includes a latch. The second input circuit configured to receive an input for a second memory access based on the second clock. The second input circuit includes a flip-flop.

Abstract translation: 用于操作所提供的存储器的存储器和方法。 在一个方面，存储器可以是PDP存储器。 存储器包括控制电路，该控制电路经配置以响应于访问周期的时钟的边沿而产生第一时钟和第二时钟。 第一输入电路被配置为基于第一时钟接收用于第一存储器访问的输入。 第一输入电路包括锁存器。 第二输入电路被配置为基于第二时钟接收用于第二存储器访问的输入。 第二输入电路包括触发器。

公开(公告)号：US09252765B2

公开(公告)日：2016-02-02

申请号：US14472953

申请日：2014-08-29

Applicant: QUALCOMM Incorporated

Inventor： Esin Terzioglu ,  Gregory Ameriada Uvieghara ,  Sei Seung Yoon ,  Balachander Ganesan ,  Anil Chowdary Kota

IPC: G11C8/08 ,  H03K17/22 ,  G11C7/12 ,  G11C17/18 ,  H03K17/081 ,  H03K19/003 ,  G11C7/00 ,  H03K17/687 ,  G11C13/00

CPC classification number: H03K17/223 ,  G11C7/00 ,  G11C7/12 ,  G11C8/08 ,  G11C13/0069 ,  G11C17/18 ,  H03K17/08104 ,  H03K17/6872 ,  H03K19/00315 ,  H03K2217/0018 ,  H03K2217/0063 ,  H03K2217/0072

Abstract: A dual-mode PMOS transistor is disclosed that has a first mode of operation in which a switched n-well for the dual-mode PMOS transistor is biased to a high voltage. The dual-mode PMOS transistor has a second mode of operation in which the switched n-well is biased to a low voltage that is lower than the high voltage. The dual-mode PMOS transistor has a size and gate-oxide thickness each having a magnitude that cannot accommodate a permanent tie to the high voltage. An n-well voltage switching circuit biases the switched n-well to prevent voltage damage to the dual-mode PMOS transistor despite its relatively small size and thin gate-oxide thickness.

Abstract translation: 公开了一种双模式PMOS晶体管，其具有第一工作模式，其中用于双模式PMOS晶体管的开关n阱被偏置到高电压。 双模式PMOS晶体管具有第二工作模式，其中开关n阱被偏置成低于高电压的低电压。 双模式PMOS晶体管的尺寸和栅极氧化物厚度各自具有不能适应与高电压的永久连接的幅度。 n阱电压开关电路偏置开关n阱，以防止电压损坏双模PMOS晶体管，尽管其尺寸相对较小，栅极氧化物厚度较薄。