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    LOW-POWER SOURCE-SYNCHRONOUS SIGNALING
    33.
    发明公开
    LOW-POWER SOURCE-SYNCHRONOUS SIGNALING 审中-公开

    公开(公告)号：US20240021236A1

    公开(公告)日：2024-01-18

    申请号：US18222808

    申请日：2023-07-17

    Applicant: Rambus Inc.

    Inventor： Jared L. ZERBE ,  Frederick A. WARE

    IPC: G11C11/4076 ,  G06F1/04 ,  G06F13/42 ,  G11C7/10 ,  G11C7/22

    CPC classification number: G11C11/4076 ,  G06F1/04 ,  G06F13/4243 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C7/04

    Abstract: A method of operating a memory controller is disclosed. The method includes transmitting data signals to a memory device over each one of at least two parallel data links. A timing signal is sent to the memory device on a first dedicated link. The timing signal has a fixed phase relationship with the data signals. A data strobe signal is driven to the memory device on a second dedicated link. Phase information is received from the memory device. The phase information being generated internal to the memory device and based on a comparison between the timing signal and a version of the data strobe signal internally distributed within the memory device. A phase of the data strobe signal is adjusted relative to the timing signal based on the received phase information.

    MEMORY COMPONENT WITH ERROR-DETECT-CORRECT CODE INTERFACE
    34.
    发明申请
    MEMORY COMPONENT WITH ERROR-DETECT-CORRECT CODE INTERFACE 有权

    公开(公告)号：US20230086896A1

    公开(公告)日：2023-03-23

    申请号：US17956516

    申请日：2022-09-29

    Applicant: Rambus Inc.

    Inventor： Frederick A. WARE ,  Brent S. HAUKNESS ,  Lawrence LAI

    IPC: G06F11/10

    Abstract: A memory component internally generates and stores the check bits of error detect and correct code (EDC). In a first mode, during a read transaction, the check bits are sent to the memory controller along with the data on the data mask (DM) signal lines. In a second mode, an unmasked write transaction is defined where the check bits are sent to the memory component on the data mask signal lines. In a third mode, a masked write transaction is defined where at least a portion of the check bits are sent from the memory controller on the data signal lines coincident with an asserted data mask signal line. By sending the check bits along with the data, the EDC code can be used to detect and correct errors that occur between the memory component and the memory controller.

    ADJUSTABLE ACCESS ENERGY AND ACCESS LATENCY MEMORY SYSTEM AND DEVICES
    35.
    发明申请
    ADJUSTABLE ACCESS ENERGY AND ACCESS LATENCY MEMORY SYSTEM AND DEVICES 有权

    公开(公告)号：US20220357846A1

    公开(公告)日：2022-11-10

    申请号：US17831576

    申请日：2022-06-03

    Applicant: Rambus Inc.

    Inventor： Frederick A. WARE ,  John Eric LINSTADT

    IPC: G06F3/06 ,  G11C11/4091 ,  G11C11/4076 ,  G11C7/06 ,  G11C7/22 ,  G11C7/18 ,  G11C11/4097

    Abstract: Same sized blocks of data corresponding to a single read/write command are stored in the same memory array of a memory device, but using different formats. A first one of these formats spreads the data in the block across a larger number of memory subarrays (a.k.a., memory array tiles—MATs) than a second format. In this manner, the data blocks stored in the first format can be accessed with lower latency than the blocks stored in the second format because more data can be read from the array simultaneously. In addition, since the data stored in the second format is stored in fewer subarrays, it takes less energy to read a block stored in the second format. Thus, a system may elect, on a data block by data block basis, whether to conserve power or improve speed.

    LOW-POWER SOURCE-SYNCHRONOUS SIGNALING
    36.
    发明申请
    LOW-POWER SOURCE-SYNCHRONOUS SIGNALING 有权

    公开(公告)号：US20220130445A1

    公开(公告)日：2022-04-28

    申请号：US17521379

    申请日：2021-11-08

    Applicant: Rambus Inc.

    Inventor： Jared L. ZERBE ,  Frederick A. WARE

    IPC: G11C11/4076 ,  G06F1/04 ,  G06F13/42 ,  G11C7/10 ,  G11C7/22

    Abstract: A method of operating a memory controller is disclosed. The method includes transmitting data signals to a memory device over each one of at least two parallel data links. A timing signal is sent to the memory device on a first dedicated link. The timing signal has a fixed phase relationship with the data signals. A data strobe signal is driven to the memory device on a second dedicated link. Phase information is received from the memory device. The phase information being generated internal to the memory device and based on a comparison between the timing signal and a version of the data strobe signal internally distributed within the memory device. A phase of the data strobe signal is adjusted relative to the timing signal based on the received phase information.

    SERIALIZING AND DESERIALIZING STAGE TESTING
    37.
    发明申请
    SERIALIZING AND DESERIALIZING STAGE TESTING 有权

    公开(公告)号：US20210248031A1

    公开(公告)日：2021-08-12

    申请号：US16973142

    申请日：2019-06-14

    Applicant: Rambus Inc.

    Inventor： Angus William McLAREN ,  Robert A. HEATON ,  Aaron ALI ,  Frederick A. WARE

    IPC: G06F11/10 ,  H03M13/09

    Abstract: A first serializing stage is provided with a stream of data words composed of sub-words that each have values that associate each of the sub-words with the same error detection code value. For example, the values selected for each sub-word may each be associated with even parity. One or more serializing stages time-multiplex the sub-words into a stream of sub-word sized data. At the serializing stage that receives sub-word sized data stream, the data is checked to determine whether any of the sub-words is no longer associated with the error detection code value. Serializing/deserializing stages are selectively controlled to replace one or more data bits from a word being serialized/deserialized with an error detecting code value (e.g., parity). A subsequent serializing/deserializing stage is enabled to use the inserted error detecting code values and the data in the received words to determine whether an error has occurred.

    MEMORY SUBSYSTEM FOR A CRYOGENIC DIGITAL SYSTEM
    38.
    发明申请
    MEMORY SUBSYSTEM FOR A CRYOGENIC DIGITAL SYSTEM 有权

    公开(公告)号：US20210096616A1

    公开(公告)日：2021-04-01

    申请号：US16634531

    申请日：2018-07-23

    Applicant: Rambus Inc.

    Inventor： Frederick A. WARE ,  John Eric LINSTADT ,  Thomas VOGELSANG

    IPC: G06F1/20 ,  H05K7/20 ,  H01L23/367

    Abstract: The embodiments herein describe technologies of cryogenic digital systems with a first component located in a first non-cryogenic temperature domain, a second component located in a second temperature domain that is lower in temperature than the first cryogenic temperature domain, and a third component located in a cryogenic temperature domain that is lower in temperature than the second cryogenic temperature domain.

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