公开(公告)号：US10128376B2

公开(公告)日：2018-11-13

申请号：US15613955

申请日：2017-06-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungin Choi ,  Changhwa Kim ,  Taegon Kim ,  Hyunchul Song

IPC: H01L27/148 ,  H01L29/80 ,  H01L29/76 ,  H01L21/00 ,  H01L21/338 ,  H01L21/337 ,  H01L29/78 ,  H01L29/06

Abstract: Semiconductor devices and methods of forming the semiconductor devices are provided. The semiconductor devices may include a substrate, a device isolation layer that defines an active region, an active fin vertically protruding from the active region of the substrate and extending in a horizontal direction, a gate structure traversing the active fin, and a source/drain contact on the active fin on a side of the gate structure. The gate structure may include a gate pattern and a capping pattern on the gate pattern, and the capping pattern may have impurities doped therein. The capping pattern may include a first part and a second part between the first part and the gate pattern. The first and second parts may have impurity concentrations different from each other.

公开(公告)号：US12113108B2

公开(公告)日：2024-10-08

申请号：US17472926

申请日：2021-09-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dohee Kim ,  Gyeom Kim ,  Jinbum Kim ,  Haejun Yu ,  Kyungin Choi ,  Kihyun Hwang ,  Seunghun Lee

IPC: H01L29/41 ,  H01L27/088 ,  H01L29/417

CPC classification number: H01L29/41775 ,  H01L27/0886

Abstract: An integrated circuit device includes a plurality of gate structures each including a gate line extending on a fin-type active region and insulation spacers on sidewalls of the gate line; a source/drain contact between first and second gate structures, and having opposing sides that are asymmetric in the first horizontal direction; and an insulation liner on sidewalls of the source/drain contact. The source/drain contact includes a lower contact portion and an upper contact portion having a horizontal extension that extends on an upper corner of the first gate structure, the insulation liner includes a first local region between the upper corner and the horizontal extension and a second local region that is farther from the substrate than the first local region, and a thickness of the first local region is greater than that of the second local region.

公开(公告)号：US20240088150A1

公开(公告)日：2024-03-14

申请号：US18300867

申请日：2023-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeondo Jung ,  Chul Kim ,  Kichul Kim ,  Gwirim Park ,  Haejun Yu ,  Chaeyeong Lee ,  Kyungin Choi

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: An integrated circuit device includes a pair of fin-type active regions, which extend in a first horizontal direction on a substrate, and a fin isolation insulator between ones of the pair of fin-type active regions to extend in a second horizontal direction that intersects with the first horizontal direction. The fin isolation insulator includes a first nitrogen-rich barrier film having at least one protrusion at a position that is higher than respective top surfaces of each of the pair of fin-type active regions with respect to the substrate, and a second nitrogen-rich barrier film, which is spaced apart from the first nitrogen-rich barrier film and is in a space defined by the first nitrogen-rich barrier film.

公开(公告)号：US11888028B2

公开(公告)日：2024-01-30

申请号：US17862453

申请日：2022-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinbum Kim ,  Dahye Kim ,  Seokhoon Kim ,  Jaemun Kim ,  Ilgyou Shin ,  Haejun Yu ,  Kyungin Choi ,  Kihyun Hwang ,  Sangmoon Lee ,  Seung Hun Lee ,  Keun Hwi Cho

IPC: H01L29/08 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/165 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H01L29/161 ,  H01L21/8234 ,  H01L29/06

CPC classification number: H01L29/0847 ,  H01L21/823814 ,  H01L21/823828 ,  H01L27/092 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/78696

Abstract: A semiconductor device includes an active pattern on a substrate, a pair of source/drain patterns on the active pattern, a channel pattern between the pair of source/drain patterns, the channel pattern including semiconductor patterns stacked to be spaced apart from each other, and a gate electrode crossing the channel pattern and extending in a first direction. One of the pair of source/drain patterns includes a first semiconductor layer and a second semiconductor layer thereon. The first semiconductor layer is in contact with a first semiconductor pattern, which is one of the stacked semiconductor patterns. The largest widths of the first semiconductor pattern, the first semiconductor layer, and the second semiconductor layer in the first direction are a first width, a second width, a third width, respectively, and the second width is larger than the first width and smaller than the third width.

公开(公告)号：US11881508B2

公开(公告)日：2024-01-23

申请号：US17843105

申请日：2022-06-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungin Choi ,  Hyunchul Song ,  Sunjung Kim ,  Taegon Kim ,  Seong Hoon Jeong

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/3115 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H10B10/00 ,  H01L21/308 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/165 ,  H01L29/08

CPC classification number: H01L29/0653 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/3105 ,  H01L21/31155 ,  H01L21/76224 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0847 ,  H10B10/12 ,  H01L21/02208 ,  H01L21/308 ,  H01L21/823821 ,  H01L29/6656 ,  H01L29/66545

Abstract: A semiconductor device includes a substrate including a first active pattern and a second active pattern, a device isolation layer filling a first trench between the first and second active patterns, the device isolation layer including a silicon oxide layer doped with helium, a helium concentration of the device isolation layer being higher than a helium concentration of the first and second active patterns, and a gate electrode crossing the first and second active patterns.

公开(公告)号：US11749754B2

公开(公告)日：2023-09-05

申请号：US17550712

申请日：2021-12-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangmoon Lee ,  Kyungin Choi ,  Seunghun Lee

IPC: H01L31/113 ,  H01L31/119 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L29/785 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/6681

Abstract: An active pattern structure includes a lower active pattern protruding from an upper surface of a substrate in a vertical direction substantially perpendicular to an upper surface of the substrate, a buffer structure on the lower active pattern, at least a portion of which may include aluminum silicon oxide, and an upper active pattern on the buffer structure.

公开(公告)号：US11532620B2

公开(公告)日：2022-12-20

申请号：US17524128

申请日：2021-11-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungin Choi ,  Dahye Kim ,  Jaemun Kim ,  Jinbum Kim ,  Seunghun Lee

IPC: H01L27/088 ,  H01L29/165 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/02 ,  H01L29/66 ,  H01L21/306 ,  H01L21/762

Abstract: Integrated circuit devices may include a fin-type active area, a semiconductor liner contacting a side wall of the fin-type active area and including a protrusion portion protruding outward from the fin-type active area in the vicinity of an edge of an upper surface of the fin-type active area, and an isolation layer spaced apart from the fin-type active area with the semiconductor liner therebetween. To manufacture the integrated circuit devices, a crystalline semiconductor layer covering the fin-type active area with a first thickness and an amorphous semiconductor layer covering the mask pattern with a second thickness may be formed, an extended crystalline semiconductor layer covering the mask pattern may be formed by crystalizing the amorphous semiconductor layer, and a semiconductor liner including a protrusion portion may be formed from the extended crystalline semiconductor layer and the crystalline semiconductor layer.

公开(公告)号：US20220246738A1

公开(公告)日：2022-08-04

申请号：US17472926

申请日：2021-09-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dohee Kim ,  Gyeom Kim ,  Jinbum Kim ,  Haejun Yu ,  Kyungin Choi ,  Kihyun Hwang ,  Seunghun Lee

IPC: H01L29/417 ,  H01L27/088

Abstract: An integrated circuit device includes a plurality of gate structures each including a gate line extending on a fin-type active region and insulation spacers on sidewalls of the gate line; a source/drain contact between first and second gate structures, and having opposing sides that are asymmetric in the first horizontal direction; and an insulation liner on sidewalls of the source/drain contact. The source/drain contact includes a lower contact portion and an upper contact portion having a horizontal extension that extends on an upper corner of the first gate structure, the insulation liner includes a first local region between the upper corner and the horizontal extension and a second local region that is farther from the substrate than the first local region, and a thickness of the first local region is greater than that of the second local region.

公开(公告)号：US11233151B2

公开(公告)日：2022-01-25

申请号：US16887900

申请日：2020-05-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangmoon Lee ,  Kyungin Choi ,  Seunghun Lee

IPC: H01L31/113 ,  H01L31/119 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/417

Abstract: An active pattern structure includes a lower active pattern protruding from an upper surface of a substrate in a vertical direction substantially perpendicular to an upper surface of the substrate, a buffer structure on the lower active pattern, at least a portion of which may include aluminum silicon oxide, and an upper active pattern on the buffer structure.

公开(公告)号：US11201087B2

公开(公告)日：2021-12-14

申请号：US16838089

申请日：2020-04-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaemun Kim ,  Gyeom Kim ,  Seung Hun Lee ,  Dahye Kim ,  Ilgyou Shin ,  Sangmoon Lee ,  Kyungin Choi

IPC: H01L21/8234 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/306 ,  H01L21/762

Abstract: A method includes forming an active pattern on a substrate, the active pattern comprising first semiconductor patterns and second semiconductor patterns, which are alternately stacked, forming a capping pattern on a top surface and a sidewall of the active pattern, performing a deposition process on the capping pattern to form an insulating layer, and forming a sacrificial gate pattern intersecting the active pattern on the insulating layer. The capping pattern has a crystalline structure and is in physical contact with sidewalls of the first semiconductor patterns and sidewalls of the second semiconductor patterns.