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    Command Sequence For First Read Solution For Memory
    33.
    发明申请
    Command Sequence For First Read Solution For Memory 审中-公开

    公开(公告)号：US20180114580A1

    公开(公告)日：2018-04-26

    申请号：US15440185

    申请日：2017-02-23

    Applicant: SanDisk Technologies LLC

    Inventor： Idan Alrod ,  Eran Sharon ,  Alon Eyal ,  Liang Pang ,  Evgeny Mekhanik

    IPC: G11C16/26 ,  G11C16/34

    CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/3418 ,  G11C16/349 ,  G11C2211/563

    Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of a memory cell can shift depending on when the read operation occurs. A command is issued for performing a conditioning operation which helps to transition the memory cells so that their threshold voltages are at predictable levels. In one approach, the conditioning operation is performed by applying a voltage pulse to one or more word lines in response to a trigger, such as detecting that a duration since a last sensing operation exceeds a threshold, detecting that a duration since a last performance of the conditioning operation exceeds a threshold, or a detecting that a read command has been issued. Moreover, the peak power consumption required to perform the conditioning operation can be reduced for various configurations of a memory device on one or more die.

    TWO-SIDED ADJACENT MEMORY CELL INTERFERENCE MITIGATION
    36.
    发明申请
    TWO-SIDED ADJACENT MEMORY CELL INTERFERENCE MITIGATION 有权

    公开(公告)号：US20220180940A1

    公开(公告)日：2022-06-09

    申请号：US17114256

    申请日：2020-12-07

    Applicant: SanDisk Technologies LLC

    Inventor： Eran Sharon ,  Idan Alrod ,  Alexander Bazarsky

    IPC: G11C16/26 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/34 ,  H01L25/065 ,  H01L23/00 ,  H01L27/11582

    Abstract: Technology for two-sided adjacent memory cell interference mitigation in a non-volatile storage system is disclosed. During reading of target memory cells, the storage system applies a suitable magnitude read pass voltage to a first unselected word line adjacent to a target word line to compensate for interference from adjacent cells on the first unselected word line while applying a suitable magnitude read reference voltage to the target word line to compensate for interference from adjacent cells on a second unselected word line on the other side of the target word line. The read pass voltage may compensate for interference due to charge being added to when programming cells on the first unselected word line after programming the target cells. The read reference voltage may compensate for interference due to charge movement near the target cells that results from charge stored in the cells on the second unselected word line.

    Convolutional low-density parity-check coding
    38.
    发明授权
    Convolutional low-density parity-check coding 有权

    公开(公告)号：US10367528B2

    公开(公告)日：2019-07-30

    申请号：US15179069

    申请日：2016-06-10

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Idan Goldenberg ,  Alexander Bazarsky ,  Stella Achtenberg ,  Ishai Ilani ,  Eran Sharon

    IPC: G06F11/10 ,  H03M13/11

    Abstract: In an illustrative example, a method includes receiving data to be processed in accordance with a convolutional low-density parity-check (CLDPC) code. The method also includes processing the data based on a parity check matrix associated with the CLDPC code. The parity check matrix includes a first portion and a second portion. The first portion includes a plurality of copies of a first sub-matrix that is associated with a first sub-code, and the second portion includes a copy of second sub-matrix that is associated with a second sub-code.

    Command sequence for first read solution for memory
    40.
    发明授权
    Command sequence for first read solution for memory 有权

    公开(公告)号：US10262743B2

    公开(公告)日：2019-04-16

    申请号：US15440185

    申请日：2017-02-23

    Applicant: SanDisk Technologies LLC

    Inventor： Idan Alrod ,  Eran Sharon ,  Alon Eyal ,  Liang Pang ,  Evgeny Mekhanik

    IPC: G11C7/00 ,  G11C16/26 ,  G11C16/34 ,  G11C16/08 ,  G11C16/04

    Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of a memory cell can shift depending on when the read operation occurs. A command is issued for performing a conditioning operation which helps to transition the memory cells so that their threshold voltages are at predictable levels. In one approach, the conditioning operation is performed by applying a voltage pulse to one or more word lines in response to a trigger, such as detecting that a duration since a last sensing operation exceeds a threshold, detecting that a duration since a last performance of the conditioning operation exceeds a threshold, or a detecting that a read command has been issued. Moreover, the peak power consumption required to perform the conditioning operation can be reduced for various configurations of a memory device on one or more die.

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