公开(公告)号：US20230326531A1

公开(公告)日：2023-10-12

申请号：US17718124

申请日：2022-04-11

Applicant: SanDisk Technologies LLC

Inventor： Yanjie Wang ,  Ohwon Kwon ,  Kou Tei ,  Tai-Yuan Tseng ,  Yasue Yamamoto ,  Yonggang Wu ,  Guirong Liang

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/24 ,  G11C16/08 ,  G11C16/16 ,  G11C16/30 ,  G11C16/34

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/08 ,  G11C16/16 ,  G11C16/30 ,  G11C16/3459 ,  H01L25/0657

Abstract: Technology is disclosed herein for a memory system having a dynamic supply voltage to sense amplifiers. In an aspect, the supply voltage has a higher magnitude when charging inhibited bit lines during a program operation and a lower magnitude when verifying/sensing memory cells. Reducing the magnitude of the supply voltage saves power and/or current. However, if the lower magnitude were used when the inhibited bit lines are charged during the program operations, some of the memory cells that should be inhibited from programming might experience at least some programming. Using the higher magnitude supply voltage during bit line charging of the program operation assures that the inhibited bit lines are charged to a sufficient voltage to keep drain side select gates of NAND strings off so that the NAND channel will boost properly to inhibit programming of such memory cells.

公开(公告)号：US11334294B2

公开(公告)日：2022-05-17

申请号：US16909467

申请日：2020-06-23

Applicant: SanDisk Technologies LLC

Inventor： Chi-Lin Hsu ,  Tai-Yuan Tseng ,  Yan Li ,  Hiroyuki Mizukoshi

IPC: G06F3/06 ,  G06F9/30 ,  G06F9/38 ,  G11C11/00 ,  G11C5/06 ,  G11C11/4072 ,  G06F8/65 ,  G11C29/16 ,  G11C5/14 ,  G11C16/28 ,  G11C11/56 ,  G11C29/46 ,  G11C16/34 ,  G11C16/24 ,  G11C16/10 ,  G11C16/08

Abstract: A non-volatile memory system comprises a memory structure and a control circuit connected to the memory structure. The control circuit includes a programmable and reprogrammable microcontroller. The microcontroller has a first processor that executes instructions to coordinate sequences of voltages applied to the memory structure by a first circuit in order to perform memory operations. The microcontroller has a second processor that executes second instructions to control a second circuit to test conditions of the non-volatile memory cells in response to the voltages applied to the memory structure. The microcontroller may have a third processor that controls the flow of the memory operation and directs the first and second processors to execute the instructions. The instructions of the various processors may be updated, which provides for flexible flow, core operation control, and condition testing.

公开(公告)号：US10908817B2

公开(公告)日：2021-02-02

申请号：US16003515

申请日：2018-06-08

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Tai-Yuan Tseng ,  Hiroyuki Mizukoshi ,  Chi-Lin Hsu ,  Yan Li

IPC: G06F3/06 ,  G11C16/10 ,  G11C16/34 ,  G11C16/26 ,  G11C11/56 ,  G11C5/06 ,  G11C16/08 ,  G11C8/12 ,  G11C7/10 ,  G11C8/08 ,  G11C16/04

Abstract: An apparatus includes a first processor that generates first control signals to control a first circuit to perform memory operations on memory cells. A first number of first physical signal lines delivers the first control signals to a conversion circuit. A second number of second physical signal lines delivers converted control signals to the first circuit. The conversion circuit is coupled by the first number of first physical signal lines to the first processor and by the second number of second physical signal lines to the first circuit. The conversion circuit converts the first control signals to the converted control signals, and outputs the converted control signals to the first circuit. The first number of first physical signal lines is less than the second number of second physical signal lines to reduce the first number of first physical signal lines coupled between the first processor and the first circuit.

公开(公告)号：US10824376B2

公开(公告)日：2020-11-03

申请号：US15994116

申请日：2018-05-31

Applicant: SanDisk Technologies LLC

Inventor： Chi-Lin Hsu ,  Tai-Yuan Tseng ,  Yan Li ,  Hiroyuki Mizukoshi

IPC: G06F3/06 ,  G06F9/30 ,  G06F9/38 ,  G11C11/00 ,  G11C5/06 ,  G11C11/4072 ,  G06F8/65 ,  G11C29/16 ,  G11C5/14 ,  G11C16/28 ,  G11C11/56 ,  G11C29/46 ,  G11C16/34 ,  G11C16/24 ,  G11C16/10 ,  G11C16/08

Abstract: A non-volatile memory system comprises a memory structure and a control circuit connected to the memory structure. The control circuit includes a programmable and reprogrammable microcontroller. The microcontroller has a first processor that executes instructions to coordinate sequences of voltages applied to the memory structure by a first circuit in order to perform memory operations. The microcontroller has a second processor that executes second instructions to control a second circuit to test conditions of the non-volatile memory cells in response to the voltages applied to the memory structure. The microcontroller may have a third processor that controls the flow of the memory operation and directs the first and second processors to execute the instructions. The instructions of the various processors may be updated, which provides for flexible flow, core operation control, and condition testing.

公开(公告)号：US20200234768A1

公开(公告)日：2020-07-23

申请号：US16283464

申请日：2019-02-22

Applicant: SanDisk Technologies LLC

Inventor： Lei Lin ,  Zhuojie Li ,  Tai-Yuan Tseng ,  Henry Chin ,  Gerrit Jan Hemink

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/34

Abstract: Techniques are provided for predictively programming of non-volatile memory, which may reduce the number of verify operations. In one aspect, a programming circuit is configured to program memory cells to a verify low voltage and to program a set of the memory cells to target states. The set comprises memory cells having a threshold voltage between the verify low voltage and a verify high voltage. To program the set of the memory cells to the target states, the programming circuit is configured to apply two or more program pulses to memory cells in the set without verifying whether the memory cells have reached their respective target states, including: apply a first and second program enable voltages to the bit lines associated with the memory cells having different strengths.

公开(公告)号：US10366739B2

公开(公告)日：2019-07-30

申请号：US15627947

申请日：2017-06-20

Applicant: SanDisk Technologies LLC

Inventor： Anirudh Amarnath ,  Tai-Yuan Tseng

IPC: G11C16/06 ,  G11C11/4091 ,  G11C11/4094 ,  G11C16/26 ,  G11C7/06 ,  G11C7/08 ,  G11C7/12 ,  G11C11/56 ,  G11C16/08 ,  G11C16/24 ,  G11C16/32 ,  G11C11/24 ,  G11C16/04 ,  G11C16/30

Abstract: A circuit includes selected sense circuits configured to be connected to selected bit lines and unselected sense circuits configured to be connected to unselected bit lines during a sense operation. A voltage supply circuit may supply a selected pulse and an unselected pulse to the selected and unselected sense circuits. The selected sense circuits may pass the selected pulse to associated charge-storing circuits, and reject the unselected pulse. The unselected sense circuits may pass the unselected pulse to associated charge-storing circuits, and reject the selected pulse. In addition, voltage-setting circuitry may set sense voltages in the unselected sense circuits to a pre-sense level that matches the pre-sense level of communication voltages in the unselected sense circuits.

公开(公告)号：US20180197586A1

公开(公告)日：2018-07-12

申请号：US15625848

申请日：2017-06-16

Applicant: SanDisk Technologies LLC

Inventor： Qui Nguyen ,  Alexander Chu ,  Kenneth Louie ,  Anirudh Amarnath ,  Jixin Yu ,  Yen-Lung Jason Li ,  Tai-Yuan Tseng ,  Jong Yuh

IPC: G11C8/08 ,  G11C5/06 ,  H01L27/112 ,  G11C8/10 ,  G06F13/40

CPC classification number: G11C8/08 ,  G06F13/4072 ,  G11C5/06 ,  G11C8/10 ,  G11C8/14 ,  G11C16/08 ,  H01L27/112 ,  H01L27/11575 ,  H01L27/11582

Abstract: Apparatuses, systems, and methods are disclosed for three-dimensional non-volatile memory. A stack of word line layers includes word lines for a three-dimensional non-volatile memory array. A stack of word line layers may include a plurality of tiers. Word line switch transistors transfer word line bias voltages to the word lines. Word line contact regions couple word line switch transistors to word lines. A word line contact region includes a stepped structure for a tier of word line layers. A level region separates a word line contact region for a first tier from a word line contact region for a second tier.