公开(公告)号：US20200295149A1

公开(公告)日：2020-09-17

申请号：US16450149

申请日：2019-06-24

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Balaji PADMANABHAN ,  Prasad VENKATRAMAN ,  Zia HOSSAIN ,  Donald ZAREMBA ,  Gordon M. GRIVNA ,  Alexander YOUNG

IPC: H01L29/423 ,  H01L21/762

Abstract: Systems and methods of the disclosed embodiments include an electronic device that has a gate electrode for supplying a gate voltage, a source, a drain, and a channel doped to enable a current to flow from the drain to the source when a voltage is applied to the gate electrode. The electronic device may also include a gate insulator between the channel and the gate electrode. The gate insulator may include a first gate insulator section comprising a first thickness, and a second gate insulator section comprising a second thickness that is less than the first thickness. The gate insulator sections thereby improve the safe operating area by enabling the current to flow through the second gate insulator section at a lower voltage than the first gate insulator section.

公开(公告)号：US20190393088A1

公开(公告)日：2019-12-26

申请号：US16405168

申请日：2019-05-07

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Gordon M. GRIVNA

IPC: H01L21/78 ,  H01L21/3065 ,  H01L21/67

Abstract: A method for processing electronic die includes providing a substrate having a plurality of electronic die formed as part of the substrate and separated from each other by spaces. The method includes placing the substrate onto a first carrier substrate. The method includes plasma etching the substrate through the spaces to form singulation lines adjacent the plurality of electronic die. The method includes exposing the plurality of electronic die to solvent vapors, such as heated solvent vapors, under reduced pressure to reduce the presence of residual contaminants resulting from the plasma etching step.

公开(公告)号：US20190058055A1

公开(公告)日：2019-02-21

申请号：US15884773

申请日：2018-01-31

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Meng-Chia LEE ,  Ralph N. WALL ,  Mingjiao LIU ,  Shamsul Arefin KHAN ,  Gordon M. GRIVNA

IPC: H01L29/739 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06

Abstract: In a general aspect, an insulated gate bipolar transistor (IGBT) device can include an active region, an inactive region and a trench extending along a longitudinal axis in the active region. The IGBT can also include a first mesa defining a first sidewall of the trench and in parallel with the trench and a second mesa defining a second sidewall of the trench and in parallel with the trench. At least a portion of the first mesa can include an active segment of the IGBT device, and at least a portion of the second mesa can include an inactive segment of the IGBT device.

公开(公告)号：US20190035886A1

公开(公告)日：2019-01-31

申请号：US16134936

申请日：2018-09-18

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Gordon M. GRIVNA ,  Steven M. ETTER ,  Hiroyuki SUZUKI ,  Miki ICHIYANAGI ,  Toshihiro HACHIYANAGI

IPC: H01L29/06 ,  H01L49/02 ,  H01L29/78 ,  H01L29/40 ,  H01L21/762

CPC classification number: H01L29/0649 ,  H01L21/76232 ,  H01L21/764 ,  H01L28/10 ,  H01L29/0692 ,  H01L29/401 ,  H01L29/407 ,  H01L29/408 ,  H01L29/7811 ,  H01L29/7813

Abstract: An electronic device can include a substrate and an insulating structure. In an aspect, an anchor can include a portion of the substrate that extends into the insulating structure or a portion of the insulating structure that extends into the substrate. In another aspect, a process of forming an electronic device can include patterning a substrate to define a trench and a first anchor; and forming an insulating structure within the trench and adjacent to the first anchor. In a further aspect, a process of forming an electronic device can include patterning a substrate to define a trench having a sidewall and a first pillar spaced apart from the sidewall; doping the first pillar to change a conductivity type of the first pillar; and forming an insulating structure that surrounds the first pillar.

公开(公告)号：US20180261549A1

公开(公告)日：2018-09-13

申请号：US15452888

申请日：2017-03-08

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Gordon M. GRIVNA

IPC: H01L23/544 ,  H01L21/78 ,  H01L23/58

Abstract: A semiconductor substrate contains a plurality of openings extending partially into a surface of the semiconductor substrate. A conductive layer is formed with a first portion of the conductive layer over a remaining portion of the surface of the semiconductor substrate between the openings and a second portion of the conductive layer in the openings. The remaining portion of the surface of the semiconductor substrate is removed to lift-off the first portion of the conductive layer while leaving the second portion of the conductive layer in the openings. The semiconductor substrate is singulated to separate the semiconductor die leaving the second portion of the conductive layer over a surface of the semiconductor die. Alternatively, a plurality of openings is formed over each semiconductor die. A conductive layer is formed over a remaining portion of the surface of the semiconductor substrate between the openings and into the openings.

公开(公告)号：US20180254259A1

公开(公告)日：2018-09-06

申请号：US15446182

申请日：2017-03-01

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Gordon M. GRIVNA

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/78 ,  H01L21/683 ,  H01L23/31

CPC classification number: H01L24/96 ,  H01L21/561 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3114 ,  H01L24/05 ,  H01L24/13 ,  H01L2221/68327 ,  H01L2224/0401 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/13026 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/014

Abstract: A semiconductor substrate contains a plurality of semiconductor die with a saw street between the semiconductor die. A plurality of bumps is formed over a first surface of the semiconductor die. An insulating layer is formed over the first surface of the semiconductor die between the bumps. A portion of a second surface of the semiconductor die is removed and a conductive layer is formed over the remaining second surface. The semiconductor substrate is disposed on a dicing tape, the semiconductor substrate is singulated through the saw street while maintaining position of the semiconductor die, and the dicing tape is expanded to impart movement of the semiconductor die and increase a space between the semiconductor die. An encapsulant is deposited over the semiconductor die and into the space between the semiconductor die. A channel is formed through the encapsulant between the semiconductor die to separate the semiconductor die.

公开(公告)号：US20170084687A1

公开(公告)日：2017-03-23

申请号：US15252009

申请日：2016-08-30

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Gordon M. GRIVNA ,  Steve M. ETTER ,  Hiroyuki SUZUKI ,  Miki ICHIYANAGI ,  Toshihiro HACHIYANAGI

IPC: H01L29/06 ,  H01L21/762

CPC classification number: H01L29/0649 ,  H01L21/76232 ,  H01L28/10 ,  H01L29/0692 ,  H01L29/401 ,  H01L29/407 ,  H01L29/408 ,  H01L29/7811 ,  H01L29/7813

Abstract: An electronic device can include a substrate and an insulating structure. In an aspect, an anchor can include a portion of the substrate that extends into the insulating structure or a portion of the insulating structure that extends into the substrate. In another aspect, a process of forming an electronic device can include patterning a substrate to define a trench and a first anchor; and forming an insulating structure within the trench and adjacent to the first anchor. In a further aspect, a process of forming an electronic device can include patterning a substrate to define a trench having a sidewall and a first pillar spaced apart from the sidewall; doping the first pillar to change a conductivity type of the first pillar; and forming an insulating structure that surrounds the first pillar.

公开(公告)号：US20160379850A1

公开(公告)日：2016-12-29

申请号：US15248382

申请日：2016-08-26

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Gordon M. GRIVNA

IPC: H01L21/67 ,  H01L21/78 ,  H01L21/683

CPC classification number: H01L21/67092 ,  H01L21/67103 ,  H01L21/67132 ,  H01L21/67144 ,  H01L21/6836 ,  H01L21/78 ,  H01L2221/68327 ,  Y02P80/30

Abstract: In one embodiment, die are singulated from a wafer having a back layer by placing the wafer onto a first carrier substrate with the back layer adjacent the carrier substrate, forming singulation lines through the wafer to expose the back layer within the singulation lines, and using a mechanical device to apply localized pressure to the wafer to separate the back layer in the singulation lines. The localized pressure can be applied through the first carrier substrate proximate to the back layer, or can be applied through a second carrier substrate attached to a front side of the wafer opposite to the back layer. A support structure is used to heat and/or cool at least the first carrier-substrate while the localized pressure is applied.

Abstract translation: 在一个实施例中，通过将晶片放置在第一载体衬底上，使背面层与载体衬底相邻，将晶片放置在具有背层的晶片上，形成单晶线以暴露分离线内的背层，并使用 将局部压力施加到晶片以分离分离线中的背层的机械装置。 局部压力可以通过靠近背层的第一载体衬底施加，或者可以通过附接到与背层相对的晶片的前侧的第二载体衬底施加。 当施加局部压力时，使用支撑结构来加热和/或冷却至少第一载体衬底。

公开(公告)号：US20160284814A1

公开(公告)日：2016-09-29

申请号：US15176603

申请日：2016-06-08

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Gordon M. GRIVNA ,  Ali SALIH

IPC: H01L29/66 ,  H01L21/265 ,  H01L21/3065 ,  H01L21/304 ,  H01L21/762 ,  H01L21/306

CPC classification number: H01L29/66333 ,  H01L21/265 ,  H01L21/3043 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/76224 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/41766 ,  H01L29/66348 ,  H01L29/7397

Abstract: In one embodiment, an IGBT is formed to include a plurality of termination trenches in a termination region of the IGBT. An embodiment may include that one end of one or more termination trenches may be exposed on one surface of the semiconductor device.

Abstract translation: 在一个实施例中，IGBT形成为在IGBT的端接区域中包括多个端接沟槽。 一个实施例可以包括一个或多个终止沟槽的一端可以暴露在半导体器件的一个表面上。

公开(公告)号：US20160035599A1

公开(公告)日：2016-02-04

申请号：US14885804

申请日：2015-10-16

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Gordon M. GRIVNA ,  James M. PARSEY, JR.

IPC: H01L21/67 ,  B23P15/28 ,  B28D5/00

CPC classification number: H01L21/67092 ,  B23P15/28 ,  B28D5/0005 ,  B28D5/0011 ,  H01L21/78 ,  H01L2224/48091 ,  Y10T83/0333 ,  H01L2924/00014

Abstract: In one embodiment, a method of singulating semiconductor die from a semiconductor wafer includes forming a material on a surface of a semiconductor wafer and reducing a thickness of portions of the material. Preferably, the thickness of the material is reduced near where singulation openings are to be formed in the semiconductor wafer.

Abstract translation: 在一个实施例中，从半导体晶片分离半导体管芯的方法包括在半导体晶片的表面上形成材料并减小部分材料的厚度。 优选地，在半导体晶片中将形成切割开口的地方，材料的厚度减小。