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    Semiconductor device
    33.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US09595541B2

    公开(公告)日：2017-03-14

    申请号：US15082443

    申请日：2016-03-28

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Shunpei Yamazaki ,  Masahiko Hayakawa ,  Shinpei Matsuda ,  Daisuke Matsubayashi

    IPC: H01L29/10 ,  H01L29/12 ,  H01L27/12 ,  H01L29/786 ,  H01L29/49

    CPC classification number: H01L29/78648 ,  G02F1/1368 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/3262 ,  H01L29/045 ,  H01L29/24 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696

    Abstract: Provided is a semiconductor device including a transistor having excellent electrical characteristics (e.g., on-state current, field-effect mobility, or frequency characteristics) or a semiconductor device including a transistor with high reliability. In the channel width direction of a channel-etched transistor in which an oxide semiconductor film is between first and second gate electrodes, the first and second gate electrodes are connected to each other through an opening portion in first and second gate insulating films. In addition, the first and second gate electrodes surround the oxide semiconductor film in a cross-section in the channel width direction, with the first gate insulating film provided between the first gate electrode and the oxide semiconductor film and the second gate insulating film provided between the second gate electrode and the oxide semiconductor film. Furthermore, the channel length of the transistor is 0.5 μm or longer and 6.5 μm or shorter.

    Abstract translation: 提供了包括具有优异的电特性（例如导通电流，场效应迁移率或频率特性）的晶体管或包括具有高可靠性的晶体管的半导体器件的半导体器件。 在其中氧化物半导体膜位于第一和第二栅电极之间的沟道蚀刻晶体管的沟道宽度方向上，第一和第二栅极通过第一和第二栅极绝缘膜中的开口部彼此连接。 此外，第一和第二栅电极在沟道宽度方向的横截面中包围氧化物半导体膜，第一栅极绝缘膜设置在第一栅极和氧化物半导体膜之间，第二栅极绝缘膜设置在第二栅极绝缘膜之间 第二栅电极和氧化物半导体膜。 此外，晶体管的沟道长度为0.5μm以上且6.5μm以下。

    Sequential circuit and semiconductor device
    34.
    发明授权
    Sequential circuit and semiconductor device 有权
    顺序电路和半导体器件

    公开(公告)号：US09494830B2

    公开(公告)日：2016-11-15

    申请号：US14290263

    申请日：2014-05-29

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Shunpei Yamazaki ,  Hiroyuki Miyake ,  Kouhei Toyotaka ,  Masahiko Hayakawa ,  Daisuke Matsubayashi ,  Shinpei Matsuda

    IPC: H01L27/12 ,  G02F1/1343 ,  G02F1/1362 ,  G02F1/1368

    CPC classification number: G02F1/134309 ,  G02F1/133345 ,  G02F1/1343 ,  G02F1/136213 ,  G02F1/13624 ,  G02F1/1368 ,  G02F2001/13685 ,  H01L27/1225 ,  H01L27/127 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

    Abstract: The following semiconductor device provides high reliability and a narrower frame width. The semiconductor device includes a driver circuit and a pixel portion. The driver circuit has a first transistor including a first gate and a second gate electrically connected to each other with a semiconductor film sandwiched therebetween, and a second transistor electrically connected to the first transistor. The pixel portion includes a third transistor, a liquid crystal element, and a capacitor. The liquid crystal element includes a first transparent conductive film electrically connected to the third transistor, a second conductive film, and a liquid crystal layer. The capacitor includes the first conductive film, a third transparent conductive film, and a nitride insulating film. The nitride insulating film is positioned between the first transparent conductive film and the third transparent conductive film, and positioned between the semiconductor film and the second gate of the first transistor.

    Abstract translation: 以下半导体器件提供高可靠性和较窄的帧宽度。 半导体器件包括驱动电路和像素部分。 驱动电路具有包括第一栅极和第二栅极的第一晶体管，其中夹在其间的半导体膜彼此电连接，第二晶体管与第一晶体管电连接。 像素部分包括第三晶体管，液晶元件和电容器。 液晶元件包括与第三晶体管电连接的第一透明导电膜，第二导电膜和液晶层。 电容器包括第一导电膜，第三透明导电膜和氮化物绝缘膜。 氮化物绝缘膜位于第一透明导电膜和第三透明导电膜之间，位于第一晶体管的半导体膜和第二栅极之间。

    SEMICONDUCTOR DEVICE AND MEASUREMENT DEVICE
    35.
    发明申请
    SEMICONDUCTOR DEVICE AND MEASUREMENT DEVICE 有权
    半导体器件和测量器件

    公开(公告)号：US20140183530A1

    公开(公告)日：2014-07-03

    申请号：US14141838

    申请日：2013-12-27

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    Inventor： Shunpei Yamazaki ,  Shinpei Matsuda ,  Masashi Oota ,  Noritaka Ishihara

    IPC: H01L29/786 ,  H01L29/51

    CPC classification number: H01L29/7869 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/517 ,  H01L29/78606 ,  H01L29/78693 ,  H01L29/78696

    Abstract: A semiconductor device includes an oxide semiconductor layer over a first oxide layer; first source and drain electrodes over the oxide semiconductor layer; second source and drain electrodes over the first source and drain electrodes respectively; a second oxide layer over the first source and drain electrodes; a gate insulating layer over the second source and drain electrodes and the second oxide layer; and a gate electrode overlapping the oxide semiconductor layer with the gate insulating layer provided therebetween. The structure in which the oxide semiconductor layer is sandwiched by the oxide layers can suppress the entry of impurities into the oxide semiconductor layer. The structure in which the oxide semiconductor layer is contacting with the source and drain electrodes can prevent increasing resistance between the source and the drain comparing one in which an oxide semiconductor layer is electrically connected to source and drain electrodes through an oxide layer.

    Abstract translation: 半导体器件包括在第一氧化物层上的氧化物半导体层; 在氧化物半导体层上的第一源极和漏极; 分别在第一源极和漏极上的第二源极和漏极; 在第一源极和漏极上的第二氧化物层; 在第二源极和漏极电极和第二氧化物层上的栅极绝缘层; 并且与氧化物半导体层重叠的栅电极与设置在其间的栅极绝缘层。 氧化物半导体层被氧化物层夹持的结构可以抑制杂质进入氧化物半导体层。 氧化物半导体层与源极和漏极接触的结构可以防止源极和漏极之间的电阻增加，其中氧化物半导体层通过氧化物层与源极和漏极电连接。

    Semiconductor device, method for manufacturing the same, and electronic device
    36.
    发明授权
    Semiconductor device, method for manufacturing the same, and electronic device 有权

    公开(公告)号：US11075300B2

    公开(公告)日：2021-07-27

    申请号：US16133814

    申请日：2018-09-18

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    Inventor： Shunpei Yamazaki ,  Shinpei Matsuda

    IPC: H01L29/12 ,  H01L29/786 ,  H01L29/04 ,  H01L29/24 ,  H01L29/66

    Abstract: The semiconductor device includes a first insulating layer; a first oxide semiconductor; a first insulator containing indium, an element M (M is gallium, aluminum, titanium, yttrium, or tin), and zinc; a second oxide semiconductor; a source electrode layer; a drain electrode layer; a second insulator containing indium, the element M, and zinc; a gate insulating layer; and a gate electrode layer. The first and second oxide semiconductors each include a region with c-axis alignment. In the first and second oxide semiconductors, the number of indium atoms divided by sum of numbers of the indium atoms, element M atoms, and zinc atoms is ⅓ or more. In the first insulator, the number of zinc atoms divided by sum of the numbers of indium atoms, element M atoms, and zinc atoms is ⅓ or less.

    Semiconductor device
    38.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US10134911B2

    公开(公告)日：2018-11-20

    申请号：US15644940

    申请日：2017-07-10

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Yoshiyuki Kobayashi ,  Shinpei Matsuda ,  Daisuke Matsubayashi ,  Hiroyuki Tomisu

    IPC: H01L29/786 ,  G02F1/1368 ,  H01L21/822 ,  H01L27/06 ,  H01L29/04

    Abstract: A transistor whose channel is formed in a semiconductor having dielectric anisotropy is provided. A transistor having a small subthreshold swing value is provided. A transistor having normally-off electrical characteristics is provided. A transistor having a low leakage current in an off state is provided. A semiconductor device includes an insulator, a semiconductor, and a conductor. In the semiconductor device, the semiconductor includes a region overlapping with the conductor with the insulator positioned therebetween, and a dielectric constant of the region in a direction perpendicular to a top surface of the region is higher than a dielectric constant of the region in a direction parallel to the top surface.

    Semiconductor device, method for manufacturing the same, and electronic device
    39.
    发明授权
    Semiconductor device, method for manufacturing the same, and electronic device 有权

    公开(公告)号：US10096715B2

    公开(公告)日：2018-10-09

    申请号：US15079684

    申请日：2016-03-24

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Shunpei Yamazaki ,  Shinpei Matsuda

    IPC: H01L29/66 ,  H01L29/786 ,  H01L29/04 ,  H01L29/24

    Abstract: The semiconductor device includes a first insulating layer; a first oxide semiconductor; a first insulator containing indium, an element M (M is gallium, aluminum, titanium, yttrium, or tin), and zinc; a second oxide semiconductor; a source electrode layer; a drain electrode layer; a second insulator containing indium, the element M, and zinc; a gate insulating layer; and a gate electrode layer. The first and second oxide semiconductors each include a region with c-axis alignment. In the first and second oxide semiconductors, the number of indium atoms divided by sum of numbers of the indium atoms, element M atoms, and zinc atoms is ⅓ or more. In the first insulator, the number of zinc atoms divided by sum of the numbers of indium atoms, element M atoms, and zinc atoms is ⅓ or less.

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