公开(公告)号：US09406686B2

公开(公告)日：2016-08-02

申请号：US14528785

申请日：2014-10-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Julien Delalleau ,  Arnaud Regnier

IPC: H01L27/115 ,  H01L29/788 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  G11C16/14 ,  H01L21/3205 ,  H01L21/3213 ,  H01L29/78 ,  G11C16/04

CPC classification number: H01L29/42328 ,  G11C16/0425 ,  G11C16/14 ,  H01L21/28273 ,  H01L21/30604 ,  H01L21/32051 ,  H01L21/32133 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42336 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/7827 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/7883 ,  H01L29/7885

Abstract: The present disclosure relates to a memory cell comprising a vertical selection gate extending in a trench made in a substrate, a floating gate extending above the substrate, and a horizontal control gate extending above the floating gate, wherein the floating gate also extends above a portion of the vertical selection gate over a non-zero overlap distance. Application mainly to the production of a split gate memory cell programmable by hot-electron injection.

Abstract translation: 本公开涉及一种存储单元，其包括在衬底中形成的沟槽中延伸的垂直选择栅极，在衬底上方延伸的浮动栅极以及在浮置栅极上方延伸的水平控制栅极，其中浮动栅极还在部分 的垂直选择门在非零重叠距离上。 主要用于生产通过热电子注入可编程的分离栅极存储单元。

公开(公告)号：US20160071598A1

公开(公告)日：2016-03-10

申请号：US14810283

申请日：2015-07-27

Applicant: STMicroelectronics ( Rousset ) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/26

CPC classification number: G11C16/10 ,  G11C16/0408 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/24 ,  G11C16/26

Abstract: A method controls a memory that includes twin memory cells formed in a semiconductor substrate. Each memory cell includes a floating-gate transistor including a state control gate, in series with a select transistor that includes a vertical select control gate, common to the twin memory cells, and a source connected to an embedded source line, common to the memory cells. The drains of the floating-gate transistors of the twin memory cells are connected to a same bit line. The method includes controlling a memory cell so as to turn it on to couple the source line to a bit line coupled to the ground, during a step of programming or reading another memory cell.

Abstract translation: 一种方法控制包括形成在半导体衬底中的双存储单元的存储器。 每个存储单元包括一个浮动栅极晶体管，它包括状态控制栅极，与选择晶体管串联，该选择​​晶体管包括双存储单元共用的垂直选择控制栅极和连接到存储器共用的嵌入式源极线路的源极 细胞。 双存储单元的浮栅晶体管的漏极连接到相同的位线。 该方法包括在编程或读取另一个存储器单元的步骤期间控制存储器单元以将其导通以将源极线耦合到耦合到地的位线。

公开(公告)号：US20150348635A1

公开(公告)日：2015-12-03

申请号：US14719913

申请日：2015-05-22

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier

IPC: G11C16/14 ,  G11C16/04

CPC classification number: G11C16/14 ,  G11C16/0408 ,  G11C16/0425 ,  G11C16/0458 ,  G11C16/0475 ,  H01L27/115 ,  H01L27/11517

Abstract: The present disclosure relates to a method for controlling two twin memory cells each comprising a floating-gate transistor comprising a state control gate, in series with a select transistor comprising a select control gate common to the two memory cells, the drains of the floating-gate transistors being connected to a same bit line, the method comprising steps of programming the first memory cell by hot-electron injection, by applying a positive voltage to the bit line and a positive voltage to the state control gate of the first memory cell, and simultaneously, of applying to the state control gate of the second memory cell a positive voltage capable of causing a programming current to pass through the second memory cell, without switching it to a programmed state.

Abstract translation: 本公开涉及一种用于控制两个双存储单元的方法，每个双存储器单元包括浮置晶体管，其包括状态控制栅极，与包括两个存储单元共用的选择控制栅极的选择晶体管串联， 栅极晶体管连接到相同的位线，该方法包括以下步骤：通过对位线施加正电压并将正电压施加到第一存储单元的状态控制栅极，通过热电子注入来对第一存储单元进行编程， 并且同时向第二存储单元的状态控制栅极施加能够使编程电流通过第二存储单元的正电压，而不将其切换到编程状态。

公开(公告)号：US20150117117A1

公开(公告)日：2015-04-30

申请号：US14528785

申请日：2014-10-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Julien Delalleau ,  Arnaud Regnier

IPC: H01L27/115 ,  H01L21/3205 ,  H01L29/788 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  G11C16/14 ,  H01L21/3213

CPC classification number: H01L29/42328 ,  G11C16/0425 ,  G11C16/14 ,  H01L21/28273 ,  H01L21/30604 ,  H01L21/32051 ,  H01L21/32133 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42336 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/7827 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/7883 ,  H01L29/7885

Abstract: The present disclosure relates to a memory cell comprising a vertical selection gate extending in a trench made in a substrate, a floating gate extending above the substrate, and a horizontal control gate extending above the floating gate, wherein the floating gate also extends above a portion of the vertical selection gate over a non-zero overlap distance. Application mainly to the production of a split gate memory cell programmable by hot-electron injection.

Abstract translation: 本公开涉及一种存储单元，其包括在衬底中形成的沟槽中延伸的垂直选择栅极，在衬底上方延伸的浮动栅极以及在浮置栅极上方延伸的水平控制栅极，其中浮动栅极还在部分 的垂直选择门在非零重叠距离上。 主要用于生产通过热电子注入可编程的分离栅极存储单元。

公开(公告)号：US12125899B2

公开(公告)日：2024-10-22

申请号：US17180197

申请日：2021-02-19

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Arnaud Regnier ,  Dann Morillon ,  Franck Julien ,  Marjorie Hesse

IPC: H01L29/66 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/12 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/66568 ,  H01L21/28114 ,  H01L21/28132 ,  H01L21/823468 ,  H01L21/84 ,  H01L27/1207 ,  H01L29/41775 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/78654

Abstract: A method of manufacturing a MOS transistor includes forming a conductive first gate and forming insulating spacers along opposite sides of the gate, wherein the spacers are formed before the gate.

公开(公告)号：US10971633B2

公开(公告)日：2021-04-06

申请号：US16560810

申请日：2019-09-04

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier

IPC: H01L29/861 ,  H01L27/07 ,  H01L29/788 ,  H01L29/66

Abstract: In accordance with an embodiment of the present invention, a method of making a semiconductor device includes simultaneously etching a semiconductor layer and a conductive layer to form a self-aligned diode region disposed on an insulating layer, where the semiconductor layer has a first conductivity type. The method further includes etching through first openings of a mask layer to form first implantation surfaces on the semiconductor layer and to form a plurality of projecting regions including conductive material of the conductive layer over the semiconductor layer. The method further includes using the plurality of projecting regions as a part of a first implantation mask, performing a first implantation of dopants having a second conductivity type into the semiconductor layer, to form a sequence of PN junctions forming diodes in the semiconductor layer. The diodes vertically extend from an upper surface of the semiconductor layer to the insulating layer.

公开(公告)号：US10790293B2

公开(公告)日：2020-09-29

申请号：US16542511

申请日：2019-08-16

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier

IPC: H01L27/11563 ,  H01L21/28 ,  H01L27/1157 ,  H01L29/423 ,  G11C16/04 ,  H01L27/11536

Abstract: A memory device includes a first state transistor and a second state transistor having a common control gate. A first selection transistor is buried in the semiconductor body and coupled to the first state transistor so that current paths of the first selection transistor and first state transistor are coupled in series. A second selection transistor is buried in the semiconductor body and coupled to the second state transistor so that current paths of the second selection transistor and second state transistor are coupled in series. The first and second selection transistors have a common buried selection gate. A dielectric region is located between the common control gate and the semiconductor body. A first bit line is coupled to the first state transistor and a second bit line is coupled to the second state transistor.

公开(公告)号：US10438960B2

公开(公告)日：2019-10-08

申请号：US15810979

申请日：2017-11-13

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier

IPC: H01L27/11563 ,  H01L29/423 ,  H01L21/28 ,  H01L27/1157 ,  H01L27/11536 ,  G11C16/04

Abstract: Each memory cell is of the type with charge trapping in a dielectric interface and includes a state transistor selectable by a vertical selection transistor buried in a substrate and comprising a buried selection gate. The columns of memory cells include pairs of twin memory cells. The two selection transistors of a pair of twin memory cells have a common selection gate and the two state transistors of a pair of twin memory cells have a common control gate. The device also includes, for each pair of twin memory cells, a dielectric region situated between the control gate and the substrate and overlapping the common selection gate so as to form on either side of the selection gate the two charge-trapping dielectric interfaces respectively dedicated to the two twin memory cells.

公开(公告)号：US10354926B2

公开(公告)日：2019-07-16

申请号：US15723528

申请日：2017-10-03

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Benoît Froment ,  Stephan Niel ,  Arnaud Regnier ,  Abderrezak Marzaki

IPC: H01L21/8234 ,  H01L21/762 ,  H01L21/74 ,  H01L27/08 ,  H01L49/02 ,  H01C7/12 ,  H01L21/765 ,  H01L29/8605 ,  H01L23/522 ,  H01L29/06

Abstract: An integrated circuit includes a semiconductor substrate with an electrically isolated semiconductor well. An upper trench isolation extends from a front face of the semiconductor well to a depth located a distance from the bottom of the well. Two additional isolating zones are electrically insulated from the semiconductor well and extending inside the semiconductor well in a first direction and vertically from the front face to the bottom of the semiconductor well. At least one hemmed resistive region is bounded by the two additional isolating zones, the upper trench isolation and the bottom of the semiconductor well. Electrical contacts are electrically coupled to the hemmed resistive region.

公开(公告)号：US09876122B2

公开(公告)日：2018-01-23

申请号：US15365768

申请日：2016-11-30

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Marc Mantelli ,  Stephan Niel ,  Arnaud Regnier ,  Francesco La Rosa ,  Julien Delalleau

IPC: H01L29/788 ,  G11C16/04 ,  H01L27/115 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L27/11553 ,  G11C16/14 ,  H01L21/266 ,  H01L21/306 ,  H01L21/308 ,  H01L21/3213 ,  H01L27/11524 ,  H01L27/11521 ,  H01L27/11556

CPC classification number: H01L29/7883 ,  G11C16/0425 ,  G11C16/14 ,  H01L21/266 ,  H01L21/28273 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/32133 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11553 ,  H01L27/11556 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/788

Abstract: Various embodiments provide a memory cell that includes a vertical selection gate, a floating gate extending above the substrate, wherein the floating gate also extends above a portion of the vertical selection gate, over a non-zero overlap distance, the memory cell comprising a doped region implanted at the intersection of a vertical channel region extending opposite the selection gate and a horizontal channel region extending opposite the floating gate.