公开(公告)号：US20180026136A1

公开(公告)日：2018-01-25

申请号：US15723152

申请日：2017-10-02

Applicant: STMICROELECTRONICS, INC.

Inventor： Pierre Morin ,  Nicolas Loubet

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L27/0886 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, and source and drain regions adjacent the channel region to generate shear and normal strain on the channel region. A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, source and drain regions adjacent the channel region, and a gate over the channel region. The fin may be canted with respect to the source and drain regions to generate shear and normal strain on the channel region.

公开(公告)号：US09831342B2

公开(公告)日：2017-11-28

申请号：US14975534

申请日：2015-12-18

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Pierre Morin

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/165 ,  H01L29/15 ,  H01L29/16 ,  H01L29/161

CPC classification number: H01L29/7848 ,  H01L29/1054 ,  H01L29/155 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height.

公开(公告)号：US09806196B2

公开(公告)日：2017-10-31

申请号：US15255862

申请日：2016-09-02

Applicant: STMICROELECTRONICS, INC.

Inventor： Pierre Morin ,  Nicolas Loubet

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L27/088

CPC classification number: H01L29/7848 ,  H01L27/0886 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, and source and drain regions adjacent the channel region to generate shear and normal strain on the channel region. A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, source and drain regions adjacent the channel region, and a gate over the channel region. The fin may be canted with respect to the source and drain regions to generate shear and normal strain on the channel region.

公开(公告)号：US09660080B2

公开(公告)日：2017-05-23

申请号：US14194215

申请日：2014-02-28

Applicant: STMicroelectronics, Inc.

Inventor： Pierre Morin ,  Nicolas Loubet

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/225 ,  H01L29/165 ,  H01L29/16 ,  H01L29/161 ,  H01L29/786 ,  H01L29/10

CPC classification number: H01L27/10879 ,  H01L21/2251 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/4236 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/7825 ,  H01L29/7838 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7855 ,  H01L29/78603 ,  H01L29/78654

Abstract: Methods and structures for forming a localized, strained region of a substrate are described. Trenches may be formed at boundaries of a localized region of a substrate. An upper portion of sidewalls at the localized region may be covered with a covering layer, and a lower portion of the sidewalls at the localized region may not be covered. A converting material may be formed in contact with the lower portion of the localized region, and the substrate heated. The heating may introduce a chemical species from the converting material into the lower portion, which creates stress in the localized region. The methods may be used to form strained-channel finFETs.

公开(公告)号：US20170062426A1

公开(公告)日：2017-03-02

申请号：US14833857

申请日：2015-08-24

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Pierre Morin ,  Yann Mignot

IPC: H01L27/092 ,  H01L21/02 ,  H01L29/06 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/78 ,  H01L29/165 ,  H01L21/762

CPC classification number: H01L21/823821 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/4916 ,  H01L29/7842 ,  H01L29/785

Abstract: Integrated circuits are disclosed in which the strain properties of adjacent pFETs and nFETs are independently adjustable. The pFETs include compressive-strained SiGe on a silicon substrate, while the nFETs include tensile-strained silicon on a strain-relaxed SiGe substrate. Adjacent n-type and p-type FinFETs are separated by electrically insulating regions formed by a damascene process. During formation of the insulating regions, the SiGe substrate supporting the n-type devices is permitted to relax elastically, thereby limiting defect formation in the crystal lattice of the SiGe substrate.

Abstract translation: 公开了集成电路，其中相邻pFET和nFET的应变特性可独立调节。 pFET在硅衬底上包括压应变SiGe，而nFET在应变弛豫SiGe衬底上包括拉伸应变硅。 相邻的n型和p型FinFET由通过镶嵌工艺形成的电绝缘区域分开。 在形成绝缘区域的过程中，允许支持n型器件的SiGe衬底弹性弛豫，从而限制SiGe衬底的晶格中的缺陷形成。

公开(公告)号：US20160329253A1

公开(公告)日：2016-11-10

申请号：US14705291

申请日：2015-05-06

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  Pierre Morin

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/3105 ,  H01L21/324 ,  H01L21/308 ,  H01L21/02

CPC classification number: H01L27/1211 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02592 ,  H01L21/02598 ,  H01L21/02694 ,  H01L21/3081 ,  H01L21/31051 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/785

Abstract: A tensile strained silicon layer is patterned to form a first group of fins in a first substrate area and a second group of fins in a second substrate area. The second group of fins is covered with a tensile strained material, and an anneal is performed to relax the tensile strained silicon semiconductor material in the second group of fins and produce relaxed silicon semiconductor fins in the second area. The first group of fins is covered with a mask, and silicon-germanium material is provided on the relaxed silicon semiconductor fins. Germanium from the silicon germanium material is then driven into the relaxed silicon semiconductor fins to produce compressive strained silicon-germanium semiconductor fins in the second substrate area (from which p-channel finFET devices are formed). The mask is removed to reveal tensile strained silicon semiconductor fins in the first substrate area (from which n-channel finFET devices are formed).

Abstract translation: 图案化拉伸应变硅层以在第一基板区域中形成第一组翅片，在第二基底区域中形成第二组翅片。 第二组翅片被拉伸应变材料覆盖，并且进行退火以使第二组翅片中的拉伸应变硅半导体材料松弛，并在第二区域中产生松弛的硅半导体翅片。 第一组翅片用掩模覆盖，硅 - 锗材料设置在松散的硅半导体鳍片上。 然后将来自硅锗材料的锗驱动到松散的硅半导体鳍片中，以在第二衬底区域（从其形成p沟道finFET器件）中产生压缩应变硅 - 锗半导体鳍片。 去除掩模以在第一衬底区域（从其形成n沟道finFET器件）中露出拉伸应变硅半导体鳍片。

公开(公告)号：US09490355B2

公开(公告)日：2016-11-08

申请号：US14945936

申请日：2015-11-19

Applicant: STMicroelectronics, Inc.

Inventor： Pierre Morin ,  John Hongguang Zhang

IPC: H01L29/772 ,  H01L29/66 ,  H01L27/02 ,  H01L29/16 ,  H01L29/08 ,  H01L21/04 ,  H01L21/308 ,  H01L27/146 ,  H01L29/417 ,  H01L29/06

CPC classification number: H01L29/7722 ,  H01L21/0475 ,  H01L21/0485 ,  H01L21/308 ,  H01L27/0225 ,  H01L27/14679 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0843 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/66068 ,  H01L29/66416

Abstract: A static induction transistor is formed on a silicon carbide substrate doped with a first conductivity type. First recessed regions in a top surface of the silicon carbide substrate are filled with epitaxially grown gate regions in situ doped with a second conductivity type. Epitaxially grown channel regions in situ doped with the first conductivity type are positioned between adjacent epitaxial gate regions. Epitaxially grown source regions in situ doped with the first conductivity type are positioned on the epitaxial channel regions. The bottom surface of the silicon carbide substrate includes second recessed regions vertically aligned with the channel regions and silicided to support formation of the drain contact. The top surfaces of the source regions are silicided to support formation of the source contact. A gate lead is epitaxially grown and electrically coupled to the gate regions, with the gate lead silicided to support formation of the gate contact.

公开(公告)号：US09466718B2

公开(公告)日：2016-10-11

申请号：US14663843

申请日：2015-03-20

Applicant: STMICROELECTRONICS, INC.

Inventor： Pierre Morin ,  Nicolas Loubet

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L27/0886 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, and source and drain regions adjacent the channel region to generate shear and normal strain on the channel region. A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, source and drain regions adjacent the channel region, and a gate over the channel region. The fin may be canted with respect to the source and drain regions to generate shear and normal strain on the channel region.

Abstract translation: 半导体器件可以包括衬底，在衬底上方具有沟道区域的鳍，以及与沟道区相邻的源区和漏区，以在沟道区上产生剪切和正应变。 半导体器件可以包括衬底，在衬底上方的鳍片，其中具有沟道区域，与沟道区域相邻的源极和漏极区域以及沟道区域上的栅极。 翅片可以相对于源极和漏极区域倾斜以在沟道区域上产生剪切和正常应变。

公开(公告)号：US09466664B2

公开(公告)日：2016-10-11

申请号：US14982474

申请日：2015-12-29

Applicant: STMicroelectronics, Inc. ,  Commissariat a l'energie Atomique et Aux Energies Alternatives ,  GlobalFoundries Inc.

Inventor： Pierre Morin ,  Maud Vinet ,  Laurent Grenouillet ,  Ajey Poovannummoottil Jacob

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/283 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/10 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L29/0607 ,  H01L21/02636 ,  H01L21/283 ,  H01L21/3086 ,  H01L21/32 ,  H01L21/762 ,  H01L21/76264 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/0665 ,  H01L29/1066 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7847 ,  H01L29/7849

Abstract: Methods and structures for forming uniaxially-strained, nanoscale, semiconductor bars from a biaxially-strained semiconductor layer are described. A spatially-doubled mandrel process may be used to form a mask for patterning dense, narrow trenches through the biaxially-strained semiconductor layer. The resulting slicing of the biaxially-strained layer enhances carrier mobility and can increase device performance.

Abstract translation: 描述了从双轴应变半导体层形成单轴应变纳米级半导体条的方法和结构。 可以使用空间双倍的心轴工艺来形成用于图案化通过双轴应变半导体层的致密的窄沟槽的掩模。 所得到的双轴应变层的切片增强了载流子迁移率并且可以提高器件性能。

公开(公告)号：US09318372B2

公开(公告)日：2016-04-19

申请号：US14526053

申请日：2014-10-28

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics, Inc.

Inventor： Olivier Nier ,  Denis Rideau ,  Pierre Morin ,  Emmanuel Josse

IPC: H01L21/00 ,  H01L21/762 ,  H01L29/78 ,  H01L27/12 ,  H01L21/02

CPC classification number: H01L21/76283 ,  H01L21/02356 ,  H01L21/02532 ,  H01L21/76237 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1203 ,  H01L29/7846 ,  H01L29/7847 ,  H01L29/7849

Abstract: One or more embodiments of the disclosure concerns a method of forming a stressed semiconductor layer involving: forming, in a surface of a semiconductor structure having a semiconductor layer in contact with an insulator layer, at least two first trenches in a first direction; introducing, via the at least two first trenches, a stress in the semiconductor layer and temporally decreasing, by annealing, the viscosity of the insulator layer; and extending the depth of the at least two first trenches to form first isolation trenches in the first direction delimiting a first dimension of at least one transistor to be formed in the semiconductor structure.

Abstract translation: 本公开的一个或多个实施方案涉及形成应力半导体层的方法，包括：在具有与绝缘体层接触的半导体层的半导体结构的表面中形成沿第一方向的至少两个第一沟槽; 通过所述至少两个第一沟槽，在所述半导体层中引入应力并且通过退火来临时降低所述绝缘体层的粘度; 并且延伸所述至少两个第一沟槽的深度以在所述第一方向上形成第一隔离沟槽，所述第一隔离沟槽限定要形成在所述半导体结构中的至少一个晶体管的第一维度。