公开(公告)号：US10379254B2

公开(公告)日：2019-08-13

申请号：US14985037

申请日：2015-12-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak Marzaki ,  Yoann Goasduff ,  Virginie Bidal ,  Pascal Fornara

IPC: H01H9/02 ,  H01H37/42 ,  H01H61/013 ,  G01V7/04 ,  B81B3/00 ,  B81C1/00 ,  H01L49/02 ,  H01H37/04 ,  H01H37/32 ,  H01L21/3213 ,  H01L29/423

Abstract: A method for producing an integrated circuit pointed element is disclosed. An element has a projection with a concave part directing its concavity towards the element. The element includes a first etchable material. A zone is formed around the concave part of the element. The zone includes a second material that is less rapidly etchable than the first material for a particular etchant. The first material and the second material are etched with the particular etchant to form an open crater in the concave part and thus to form a pointed region of the element.

公开(公告)号：US10354926B2

公开(公告)日：2019-07-16

申请号：US15723528

申请日：2017-10-03

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Benoît Froment ,  Stephan Niel ,  Arnaud Regnier ,  Abderrezak Marzaki

IPC: H01L21/8234 ,  H01L21/762 ,  H01L21/74 ,  H01L27/08 ,  H01L49/02 ,  H01C7/12 ,  H01L21/765 ,  H01L29/8605 ,  H01L23/522 ,  H01L29/06

Abstract: An integrated circuit includes a semiconductor substrate with an electrically isolated semiconductor well. An upper trench isolation extends from a front face of the semiconductor well to a depth located a distance from the bottom of the well. Two additional isolating zones are electrically insulated from the semiconductor well and extending inside the semiconductor well in a first direction and vertically from the front face to the bottom of the semiconductor well. At least one hemmed resistive region is bounded by the two additional isolating zones, the upper trench isolation and the bottom of the semiconductor well. Electrical contacts are electrically coupled to the hemmed resistive region.

公开(公告)号：US20160116631A1

公开(公告)日：2016-04-28

申请号：US14985037

申请日：2015-12-30

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak Marzaki ,  Yoann Goasduff ,  Virginie Bidal ,  Pascal Fornara

IPC: G01V7/04 ,  B81C1/00 ,  H01H37/32 ,  H01L29/423 ,  B81B3/00 ,  H01H37/04 ,  H01L21/3213 ,  H01L49/02

CPC classification number: G01V7/04 ,  B81B3/001 ,  B81B2201/018 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2203/0361 ,  B81B2203/04 ,  B81C1/00111 ,  H01H9/02 ,  H01H37/04 ,  H01H37/32 ,  H01H37/42 ,  H01H61/013 ,  H01L21/32139 ,  H01L28/82 ,  H01L28/88 ,  H01L29/4238

Abstract: A method for producing an integrated circuit pointed element is disclosed. An element has a projection with a concave part directing its concavity towards the element. The element includes a first etchable material. A zone is formed around the concave part of the element. The zone includes a second material that is less rapidly etchable than the first material for a particular etchant. The first material and the second material are etched with the particular etchant to form an open crater in the concave part and thus to form a pointed region of the element.

Abstract translation: 公开了一种用于制造集成电路尖锐元件的方法。 元件具有突出部，其凹部朝向元件引导其凹面。 元件包括第一可蚀刻材料。 围绕元件的凹部形成区域。 该区域包括与用于特定蚀刻剂的第一材料不太可蚀刻的第二材料。 用特定的蚀刻剂蚀刻第一材料和第二材料，以在凹部中形成开放的凹坑，从而形成元件的尖锐区域。

公开(公告)号：US12063775B2

公开(公告)日：2024-08-13

申请号：US18484906

申请日：2023-10-11

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Abderrezak Marzaki ,  Mathieu Lisart ,  Benoit Froment

IPC: H10B20/00 ,  H01L23/00 ,  G11C16/04

CPC classification number: H10B20/367 ,  G11C16/0466 ,  H01L23/57

Abstract: The present description concerns a ROM including at least one first rewritable memory cell. In an embodiment, a method of manufacturing a read-only memory (ROM) comprising a plurality of memory cells is proposed. Each of the plurality of memory cells includes a rewritable first transistor and a rewritable second transistor. An insulated gate of the rewritable first transistor is connected to an insulated gate of the rewritable second transistor. The method includes successively depositing, on a semiconductor structure, a first insulating layer and a first gate layer, wherein the first insulating layer is arranged between the semiconductor structure and the first gate layer, wherein the rewritable second transistor further includes a well-formed between an associated first insulating layer and the semiconductor structure, and wherein the rewritable first insulating layer is in direct contact with the semiconductor structure; and successively depositing a second insulating layer and a second gate layer.

公开(公告)号：US12035522B2

公开(公告)日：2024-07-09

申请号：US17700323

申请日：2022-03-21

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Franck Melul ,  Abderrezak Marzaki ,  Madjid Akbal

IPC: H10B41/35 ,  G11C16/16 ,  G11C16/26 ,  G11C16/34 ,  H01L21/28 ,  H01L29/66 ,  H01L29/788 ,  H10B41/10

CPC classification number: H10B41/35 ,  G11C16/16 ,  G11C16/26 ,  G11C16/34 ,  H01L29/66825 ,  H01L29/7884 ,  H01L29/40114 ,  H01L29/7883 ,  H10B41/10

Abstract: In an embodiment a memory cell includes a first doped well of a first conductivity type in contact with a second doped well of a second conductivity type, the second conductivity type being opposite to the first conductivity type, a third doped well of the second conductivity type in contact with a fourth doped well of the first conductivity type, a first wall in contact with the second and fourth wells, the first wall including a conductive or semiconductor core and an insulating sheath, a stack of layers including a first insulating layer, a first semiconductor layer, a second insulating layer and a second semiconductor layer at least partially covering the second and fourth wells and a third semiconductor layer located below the second and fourth wells and the first wall.

公开(公告)号：US20240040781A1

公开(公告)日：2024-02-01

申请号：US18484906

申请日：2023-10-11

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Abderrezak Marzaki ,  Mathieu Lisart ,  Benoit Froment

IPC: H10B20/00

CPC classification number: H10B20/367 ,  H01L23/57

Abstract: The present description concerns a ROM including at least one first rewritable memory cell. In an embodiment, a method of manufacturing a read-only memory (ROM) comprising a plurality of memory cells is proposed. Each of the plurality of memory cells includes a rewritable first transistor and a rewritable second transistor. An insulated gate of the rewritable first transistor is connected to an insulated gate of the rewritable second transistor. The method includes successively depositing, on a semiconductor structure, a first insulating layer and a first gate layer, wherein the first insulating layer is arranged between the semiconductor structure and the first gate layer, wherein the rewritable second transistor further includes a well-formed between an associated first insulating layer and the semiconductor structure, and wherein the rewritable first insulating layer is in direct contact with the semiconductor structure; and successively depositing a second insulating layer and a second gate layer.

公开(公告)号：US11710711B2

公开(公告)日：2023-07-25

申请号：US17351930

申请日：2021-06-18

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak Marzaki ,  Mathieu Lisart

IPC: H01L23/00 ,  G06F21/87 ,  H04N19/44 ,  H01L27/02 ,  G06F21/75

CPC classification number: H01L23/576 ,  G06F21/75 ,  G06F21/87 ,  H01L23/57 ,  H01L27/0207 ,  H04N19/44

Abstract: An integrated circuit includes a first domain supplied with power at a first supply voltage. A first transistor comprising in the first domain includes a first gate region and a first gate dielectric region. A second domain is supply with power at a second supply voltage and includes a second transistor having a second gate region and a second gate dielectric region, the second gate region being biased at a voltage that is higher than the first supply voltage. The first and second gate dielectric regions have the same composition, wherein that composition configures the first transistor in a permanently turned off condition in response to a gate bias voltage lower than or equal to the first supply voltage. The second transistor is a floating gate memory cell transistor, with the second gate dielectric region located between the floating and control gates.

公开(公告)号：US11640921B2

公开(公告)日：2023-05-02

申请号：US17068112

申请日：2020-10-12

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Franck Julien ,  Abderrezak Marzaki

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/311 ,  H01L25/16 ,  H01L25/18

Abstract: Trenches of different depths in an integrated circuit are formed by a process utilizes a dry etch. A first stop layer is formed over first and second zones of the substrate. A second stop layer is formed over the first stop layer in only the second zone. A patterned mask defines the locations where the trenches are to be formed. The dry etch uses the mask to etch in the first zone, in a given time, through the first stop layer and then into the substrate down to a first depth to form a first trench. This etch also, at the same time, etch in the second zone through the second stop layer, and further through the first stop layer, and then into the substrate down to a second depth to form a second trench. The second depth is shallower than the first depth.

公开(公告)号：US11626365B2

公开(公告)日：2023-04-11

申请号：US17226324

申请日：2021-04-09

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Crolles 2) SAS

Inventor： Abderrezak Marzaki ,  Arnaud Regnier ,  Stephan Niel

IPC: H01L23/522 ,  H01L49/02 ,  H01L27/11524

Abstract: First and second wells are formed in a semiconductor substrate. First and second trenches in the first second wells, respectively, each extend vertically and include a central conductor insulated by a first insulating layer. A second insulating layer is formed on a top surface of the semiconductor substrate. The second insulating layer is selectively thinned over the second trench. A polysilicon layer is deposited on the second insulating layer and then lithographically patterned to form: a first polysilicon portion over the first well that is electrically connected to the central conductor of the first trench to form a first capacitor plate, a second capacitor plate formed by the first well; and a second polysilicon portion over the second well forming a floating gate electrode of a floating gate transistor of a memory cell having an access transistor whose control gate is formed by the central conductor of the second trench.

公开(公告)号：US20230085284A1

公开(公告)日：2023-03-16

申请号：US17993067

申请日：2022-11-23

Applicant: STMicroelectronics ( Rousset) SAS

Inventor： Abderrezak Marzaki ,  Yoann Goasduff ,  Virginie Bidal ,  Pascal Fornara

IPC: G01V7/04 ,  B81B3/00 ,  B81C1/00 ,  H01L49/02 ,  H01H37/04 ,  H01H37/32 ,  H01L21/3213 ,  H01L29/423

Abstract: A method for detecting orientation of an integrated circuit is disclosed. The method includes moving, in response to a gravitational force, a mobile metallic piece in an evolution zone of a housing. The housing is formed in an interconnect region of the integrated circuit. The housing includes walls defining the evolution zone. The walls are formed within multiple metallization levels of the interconnect region. The walls include a floor wall and a ceiling wall. At least one of the floor wall and ceiling wall incorporate a pointed element directing its pointed region towards the mobile metallic piece. The pointed element delimits an open crater in a concave part of a projection. The method further includes creating an electrical signal by movement of the mobile metallic piece at a plurality of electrically conducting elements positioned at boundary points of the evolution zone and detecting the electrical signal by a detector.