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31.发明授权公开(公告)号：US09349490B2
公开(公告)日：2016-05-24
申请号：US14597824
申请日：2015-01-15
发明人： Marcella Carissimi , Marco Pasotti
IPC分类号： G11C29/00 , G11C29/52 , G11C7/18 , G11C11/56 , G11C16/04 , G11C16/26 , G11C16/28 , G06F11/10
CPC分类号： G11C29/52 , G06F11/1048 , G11C7/18 , G11C11/5642 , G11C16/0441 , G11C16/26 , G11C16/28 , G11C2211/4013
摘要： A differential memory device includes of memory locations having a direct memory cell and a complementary memory cell. A corresponding method includes receiving a request of reading a selected data word associated with a selected code word, reading a differential code word representing a differential version of the selected code word, verifying the differential code word according to an error correction code, setting the selected data word according to the differential code word in response to a positive verification. The method further includes reading at least one single-ended code word representing a single-ended version of the selected code word, verifying the single-ended code word according to the error correction code, and setting the selected data word according to the single-ended code word in response to a negative verification of the differential code word and to a positive verification of the single-ended code word.
摘要翻译： 差分存储器件包括具有直接存储单元和补充存储单元的存储单元。 相应的方法包括接收读取与所选码字相关联的所选数据字的请求，读取表示所选码字的差分版本的差分码字，根据纠错码验证差分码字，设置所选择的码字 数据字根据差分代码字响应积极的验证。 该方法还包括读取表示所选码字的单端版本的至少一个单端码字，根据纠错码验证单端码字，并根据单频码字单位设置所选择的数据字， 响应于对差分代码字的否定验证和对单端代码字的肯定验证，结束代码字。
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公开(公告)号：US20150235686A1
公开(公告)日：2015-08-20
申请号：US14183225
申请日：2014-02-18
发明人： Marco Pasotti , Abhishek Lal , Rajat Kulshrestha
摘要： According to various embodiments described herein, a circuit includes a decode logic circuit, a buffer coupled to the decode logic, a positive level shifter with an input coupled to receive address signals and an output coupled to the buffer, and a negative level shifter with an input coupled to receive the address signals and an output coupled to the buffer.
摘要翻译： 根据本文描述的各种实施例，电路包括解码逻辑电路，耦合到解码逻辑的缓冲器，具有耦合以接收地址信号的输入和耦合到缓冲器的输出的正电平移位器，以及负电平移位器，具有 输入耦合以接收地址信号和耦合到缓冲器的输出。
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公开(公告)号：US20240339917A1
公开(公告)日：2024-10-10
申请号：US18746752
申请日：2024-06-18
CPC分类号： H02M1/0045 , G05F1/575 , H02M3/073 , G11C13/0004 , G11C13/0038
摘要： A voltage regulator receives a reference voltage and generates a regulated voltage using a MOSFET having a gate terminal configured to receive a control voltage. A charge pump receives the regulated voltage and generates a charge pump voltage in response to an enable signal and a clock signal generated in response to the enable signal. The voltage regulator further includes a first switched capacitor circuit coupled to the gate terminal and configured to selectively charge a first capacitor with a first current and impose a first voltage drop on the control voltage in response to assertion of the enable signal. The voltage regulator also includes a second switched capacitor circuit coupled to the gate terminal and configured to selectively charge a second capacitor with a second current and impose a second voltage drop on the control voltage in response to one logic state of the clock signal.
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公开(公告)号：US20230238873A1
公开(公告)日：2023-07-27
申请号：US17582431
申请日：2022-01-24
CPC分类号： H02M1/0045 , H02M3/073 , G11C13/0004
摘要： A voltage regulator receives a reference voltage and generates a regulated voltage using a MOSFET having a gate terminal configured to receive a control voltage. A charge pump receives the regulated voltage and generates a charge pump voltage in response to an enable signal and a clock signal generated in response to the enable signal. The voltage regulator further includes a first switched capacitor circuit coupled to the gate terminal and configured to selectively charge a first capacitor with a first current and impose a first voltage drop on the control voltage in response to assertion of the enable signal. The voltage regulator also includes a second switched capacitor circuit coupled to the gate terminal and configured to selectively charge a second capacitor with a second current and impose a second voltage drop on the control voltage in response to one logic state of the clock signal.
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公开(公告)号：US10139850B2
公开(公告)日：2018-11-27
申请号：US15887323
申请日：2018-02-02
发明人： Marco Pasotti , Laura Capecchi , Riccardo Zurla
摘要： A current mirror includes an input transistor and an output transistor, wherein the sources of the input and output transistor are connected to a supply voltage node. The gates of the input and output transistors are connected through a switch. A first current source is coupled to the input transistor to provide an input current. A copy transistor has a source connected to the supply node and a gate connected to the gate of the input transistor at a mirror node. A second current source is coupled to the copy transistor to provide a copy current. A source-follower transistor has its source connected to the mirror node and its gate connected to the drain of the copy transistor. Charge sharing at the mirror node occurs in response to actuation of the switch and the source-follower transistor is turned on in response thereto to discharge the mirror node.
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公开(公告)号：US10109329B2
公开(公告)日：2018-10-23
申请号：US15471028
申请日：2017-03-28
摘要： A non-volatile memory of a complementary type includes sectors of memory cells, with each cell formed by a direct memory cell and a complementary memory cell. Each sector is in a non-written condition when the corresponding memory cells are in equal states and is in a written condition wherein each location thereof stores a first logic value or a second logic value when the memory cells of the location are in a first combination of different states or in a second combination of different states, respectively. A sector is selected and a determination is made as to a number of memory cells in the programmed state and a number of memory cells in the erased state. From this information, the condition of the selected sector is identified from a comparison between the number of memory cells in the programmed state and the number of memory cells in the erased state.
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公开(公告)号：US20180188763A1
公开(公告)日：2018-07-05
申请号：US15887323
申请日：2018-02-02
发明人： Marco Pasotti , Laura Capecchi , Riccardo Zurla
IPC分类号： G05F3/26
CPC分类号： G05F3/26
摘要： A current mirror includes an input transistor and an output transistor, wherein the sources of the input and output transistor are connected to a supply voltage node. The gates of the input and output transistors are connected through a switch. A first current source is coupled to the input transistor to provide an input current. A copy transistor has a source connected to the supply node and a gate connected to the gate of the input transistor at a mirror node. A second current source is coupled to the copy transistor to provide a copy current. A source-follower transistor has its source connected to the mirror node and its gate connected to the drain of the copy transistor. Charge sharing at the mirror node occurs in response to actuation of the switch and the source-follower transistor is turned on in response thereto to discharge the mirror node.
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公开(公告)号：US09991000B2
公开(公告)日：2018-06-05
申请号：US15476618
申请日：2017-03-31
CPC分类号： G11C16/24 , G11C7/065 , G11C11/161 , G11C11/1655 , G11C11/1673 , G11C13/0004 , G11C13/0026 , G11C13/0033 , G11C13/0035 , G11C13/004 , G11C13/0064 , G11C16/10 , G11C16/26 , G11C16/28 , G11C16/3427 , G11C16/349 , G11C2013/0042 , G11C2013/0054 , G11C2013/0066
摘要： In accordance with an embodiment, a circuit includes a sense amplifier circuit configured to sense a difference between a first current based on a direct memory bit and a second current based on a complementary memory bit. The direct memory bit is coupled to a first input of the sense amplifier circuit, and the complementary memory bit is coupled to a second input of the sense amplifier circuit. A controller is configured to, during a sense operation, selectively add a first margin current to the first current, and during the sense operation, selectively add a second margin current to the second current.
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公开(公告)号：US20180040380A1
公开(公告)日：2018-02-08
申请号：US15476618
申请日：2017-03-31
CPC分类号： G11C16/24 , G11C7/065 , G11C11/161 , G11C11/1655 , G11C11/1673 , G11C13/0004 , G11C13/0026 , G11C13/0033 , G11C13/0035 , G11C13/004 , G11C13/0064 , G11C16/10 , G11C16/26 , G11C16/28 , G11C16/3427 , G11C16/349 , G11C2013/0042 , G11C2013/0054 , G11C2013/0066
摘要： In accordance with an embodiment, a circuit includes a sense amplifier circuit configured to sense a difference between a first current based on a direct memory bit and a second current based on a complementary memory bit. The direct memory bit is coupled to a first input of the sense amplifier circuit, and the complementary memory bit is coupled to a second input of the sense amplifier circuit. A controller is configured to, during a sense operation, selectively add a first margin current to the first current, and during the sense operation, selectively add a second margin current to the second current.
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公开(公告)号：US20170178722A1
公开(公告)日：2017-06-22
申请号：US15422290
申请日：2017-02-01
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C7/065 , G11C7/08 , G11C13/0004 , G11C13/0026 , G11C13/0028 , G11C13/0061 , G11C13/0097 , G11C2013/0042 , G11C2207/002
摘要： A memory device includes an array of phase-change memory (PCM) cells and complementary PCM cells. A column decoder is coupled to the array of PCM cells and complementary PCM cells, and a sense amplifier is coupled to the column decoder. The sense amplifier includes a current integrator configured to receive first and second currents of a given PCM cell and complementary PCM cell, respectively. A current-to-voltage converter is coupled to the current integrator and is configured to receive the first and second currents, and to provide first and second voltages of the given PCM cell and complementary PCM cell to first and second nodes, respectively. A logic circuit is coupled to the first and second nodes and is configured to disable the column decoder and to discharge the bitline and complementary bitline voltages in response to the first and second voltages.
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