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    MASTER SET OF READ VOLTAGES FOR A NON-VOLATILE MEMORY (NVM) TO MITIGATE CROSS-TEMPERATURE EFFECTS
    32.
    发明申请
    MASTER SET OF READ VOLTAGES FOR A NON-VOLATILE MEMORY (NVM) TO MITIGATE CROSS-TEMPERATURE EFFECTS 有权

    公开(公告)号：US20210057024A1

    公开(公告)日：2021-02-25

    申请号：US16547925

    申请日：2019-08-22

    Applicant: Seagate Technology LLC

    Inventor： Kurt Walter Getreuer ,  Darshana H. Mehta ,  Antoine Khoueir ,  Christopher Joseph Curl

    IPC: G11C11/56 ,  G11C16/26 ,  G11C16/34 ,  G06F11/07 ,  H03M13/11

    Abstract: Method and apparatus for managing data in a non-volatile memory (NVM) of a storage device, such as a solid-state drive (SSD). In some embodiments, first data are read from the NVM using an initial set of read voltages over a selected range of cross-temperature differential (CTD) values comprising a difference between a programming temperature at which the first data are programmed to the NVM cells and a reading temperature at which the first data are subsequently read from the NVM cells. A master set of read voltages is thereafter selected that provides a lowest acceptable error rate performance level over the entirety of the CTD range, and the master set of read voltages is thereafter used irrespective of NVM temperature. In some cases, the master set of read voltages may be further adjusted for different word line addresses, program/erase counts, read counts, data aging, etc.

    Background reads to condition programmed semiconductor memory cells
    33.
    发明授权
    Background reads to condition programmed semiconductor memory cells 有权

    公开(公告)号：US10521287B2

    公开(公告)日：2019-12-31

    申请号：US16153225

    申请日：2018-10-05

    Applicant: Seagate Technology LLC

    Inventor： Antoine Khoueir ,  Stacey Secatch ,  Kevin Gomez ,  Ryan Goss

    IPC: G11C16/26 ,  G06F11/07 ,  G11C16/16 ,  G11C16/34 ,  G06F11/10 ,  G11C11/56 ,  G06F12/02 ,  G11C16/04

    Abstract: Method and apparatus for managing data in a semiconductor memory, such as but not limited to a three dimensional (3D) NAND flash memory array. In some embodiments, the memory has non-volatile memory cells arranged into addressable blocks. Each memory cell is configured to store multiple bits. A program/read control circuit programs data sets to and reads data sets from the memory cells in the addressable blocks to service a sequence of host access commands. The circuit concurrently performs background reads in conjunction with the servicing of the host access commands. The background reads result in the reading of a different data set from each of the addressable blocks over each of a succession of time intervals of selected duration. The background reads condition the memory cells prior to a first read operation associated with the host access commands.

    Fast soft data by detecting leakage current and sensing time
    34.
    发明授权
    Fast soft data by detecting leakage current and sensing time 有权
    通过检测泄漏电流和感测时间来实现快速的软数据

    公开(公告)号：US09589655B1

    公开(公告)日：2017-03-07

    申请号：US14874257

    申请日：2015-10-02

    Applicant: SEAGATE TECHNOLOGY LLC

    Inventor： Young Pil Kim ,  Antoine Khoueir ,  Namoh Hwang

    IPC: G11C16/04 ,  G11C16/26 ,  G11C16/32 ,  G11C16/34 ,  G11C11/56 ,  G11C29/00

    CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C16/32 ,  G11C16/3418 ,  G11C16/3459 ,  G11C29/00 ,  G11C29/025 ,  G11C29/026 ,  G11C29/26 ,  G11C29/28 ,  G11C29/42 ,  G11C29/50012 ,  G11C2029/1204 ,  G11C2029/5006

    Abstract: Systems and methods for low latency acquisition of soft data from a memory cell based on a sensing time and/or a leakage current are described. In one embodiment, the systems and methods may include applying a first read voltage to a word line of a page of memory cells selected by a processor of a flash memory device for a read operation, applying a pass voltage to word lines associated with one or more different pages of memory cells of the memory block, upon applying the first read voltage sensing whether a bit line of a memory cell in the selected page conducts, measuring a side effect associated with sensing whether the bit line of the memory cell in the selected page conducts, and assigning a LLR value to the memory cell as a soft LDPC input based at least in part on the measured side effect.

    Abstract translation: 描述了基于感测时间和/或泄漏电流从存储器单元低延迟获取软数据的系统和方法。 在一个实施例中，系统和方法可以包括将第一读取电压施加到由闪存器件的处理器选择的用于读取操作的存储器单元的页面的字线，将通过电压施加到与一个或多个存储器单元相关联的字线 在应用第一读取电压检测所选择的页面中的存储器单元的位线是否导通时测量与检测所选择的存储单元中的存储器单元的位线相关联的副作用的更多不同页面的存储器块的存储单元的更多不同页面 并且至少部分地基于所测量的副作用，向存储器单元分配LLR值作为软LDPC输入。

    Selecting between non-volatile memory units having different minimum addressable data unit sizes
    36.
    发明授权
    Selecting between non-volatile memory units having different minimum addressable data unit sizes 有权
    在具有不同最小可寻址数据单元大小的非易失性存储单元之间进行选择

    公开(公告)号：US09489148B2

    公开(公告)日：2016-11-08

    申请号：US13802192

    申请日：2013-03-13

    Applicant: Seagate Technology LLC

    Inventor： Ryan James Goss ,  Jon D. Trantham ,  Antoine Khoueir ,  David Scott Ebsen ,  Mark Allen Gaertner ,  Kevin Gomez

    IPC: G06F3/06

    CPC classification number: G06F3/067 ,  G06F3/061 ,  G06F3/0631 ,  G06F3/0643 ,  G06F3/0688 ,  G06F2212/7202 ,  G06F2212/7208

    Abstract: An apparatus includes a controller capable of being coupled to a host interface and a memory device. The memory device includes two or more non-hierarchical, non-volatile memory units having different minimum addressable data unit sizes. The controller is configured to at least perform determining a workload indicator of a data object being stored in the memory device via the host interface. The controller selects one of the memory units in response to the workload indicator of the data object corresponding to the minimum addressable data unit size of the selected memory unit corresponding to the workload indicator. The data object is stored in the selected memory unit in response thereto.

    Abstract translation: 一种装置包括能够耦合到主机接口和存储器装置的控制器。 存储器件包括具有不同最小可寻址数据单元尺寸的两个或更多个非分级非易失性存储器单元。 控制器被配置为经由主机接口至少执行存储在存储设备中的数据对象的工作量指示符。 控制器响应于与所述工作负载指示符对应的所选择的存储器单元的最小可寻址数据单元大小对应的数据对象的工作量指示符来选择一个存储器单元。 响应于该数据对象被存储在选择的存储单元中。

    Charge Loss Compensation Through Augmentation of Accumulated Charge in a Memory Cell
    37.
    发明申请
    Charge Loss Compensation Through Augmentation of Accumulated Charge in a Memory Cell 有权
    通过增加存储单元中累积电荷的电荷损失补偿

    公开(公告)号：US20160293250A1

    公开(公告)日：2016-10-06

    申请号：US14675056

    申请日：2015-03-31

    Applicant: Seagate Technology LLC

    Inventor： Wei Wang ,  Antoine Khoueir ,  Young Pil Kim

    IPC: G11C11/56

    CPC classification number: G11C13/0033 ,  G06F11/1068 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/107 ,  G11C16/14 ,  G11C16/3418 ,  G11C16/3431 ,  G11C2211/5621

    Abstract: Method and apparatus for managing data in a memory, such as a flash memory array. In accordance with some embodiments, a block of solid-state non-volatile memory cells are each programmed to an associated programmed state responsive to a respective amount of accumulated charge. A charge loss compensation circuit adds a relatively small amount of additional charge to the respective amount of accumulated charge in each of the memory cells to maintain the associated programmed states of the cells.

    Abstract translation: 用于管理诸如闪存阵列的存储器中的数据的方法和装置。 根据一些实施例，每个固态非易失性存储器单元的块都被编程为响应相应的累积电荷量的相关编程状态。 电荷损失补偿电路将相对少量的附加电荷添加到每个存储单元中的累积电荷的相应量，以维持单元的相关编程状态。

    Partial reprogramming of solid-state non-volatile memory cells
    38.
    发明授权
    Partial reprogramming of solid-state non-volatile memory cells 有权
    固态非易失性记忆体的部分重编程

    公开(公告)号：US09378830B2

    公开(公告)日：2016-06-28

    申请号：US13943441

    申请日：2013-07-16

    Applicant: Seagate Technology LLC

    Inventor： Antoine Khoueir ,  Varun Voddi ,  Rodney Virgil Bowman

    IPC: G11C16/12 ,  G11C16/14 ,  G11C16/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34 ,  G11C13/00

    CPC classification number: G11C16/14 ,  G11C11/5628 ,  G11C13/0033 ,  G11C13/0069 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3431

    Abstract: Method and apparatus for managing data in a memory, such as a flash memory array. In accordance with some embodiments, data are written to a set of solid-state non-volatile memory cells so that each memory cell in the set is written to an associated initial programmed state. Drift in the programmed state of a selected memory cell in the set is detected, and the selected memory cell is partially reprogrammed to return the selected memory cell to the associated initial programmed state.

    Abstract translation: 用于管理诸如闪存阵列的存储器中的数据的方法和装置。 根据一些实施例，将数据写入一组固态非易失性存储器单元，使得该组中的每个存储单元被写入相关联的初始编程状态。 检测到集合中所选择的存储器单元的编程状态的漂移，并且所选存储单元被部分重新编程以使所选择的存储单元返回到相关的初始编程状态。

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