公开(公告)号：US06266764B1

公开(公告)日：2001-07-24

申请号：US09271227

申请日：1999-03-17

申请人： Minoru Okamoto

发明人： Minoru Okamoto

IPC分类号： G06F930

CPC分类号： G06F9/3885 ,  G06F9/3851

摘要： A program controller for use in a processor operating on pipe-line principles includes: a first memory section for outputting an instruction contained in a first program including a plurality of instructions; a second memory section for outputting an instruction contained in a second program including a plurality of instructions, the first program being different from the second program; a selection section for selecting either the instruction which is output from the first memory section or the instruction which is output from the second memory section; a determination section for determining whether or not the instruction selected by the selection section is an instruction for controlling the execution order of instructions; and a control section for, if the instruction selected by the selection section is determined as an instruction for controlling the execution order of instructions, controlling the selection section so as to switch from the selected instruction to the unselected instruction of either the first memory section or the second memory section.

摘要翻译： 用于在管线原理上运行的处理器的程序控制器包括：第一存储器部分，用于输出包含在包括多个指令的第一程序中的指令; 第二存储器部分，用于输出包含在包括多个指令的第二程序中的指令，所述第一程序不同于所述第二程序; 选择部分，用于选择从第一存储器部分输出的指令或从第二存储器部分输出的指令; 确定部分，用于确定由选择部分选择的指令是否是用于控制指令的执行顺序的指令; 以及控制部分，如果由选择部分选择的指令被确定为用于控制指令的执行顺序的指令，则控制选择部分以便从所选择的指令切换到第一存储器部分或第一存储器部分的未选择指令 第二存储器部分。

公开(公告)号：US5537577A

公开(公告)日：1996-07-16

申请号：US58530

申请日：1993-05-06

申请人： Toshio Sugimura ,  Katsuhiko Ueda ,  Minoru Okamoto ,  Toshihiro Ishikawa ,  Mikako Yasutome

发明人： Toshio Sugimura ,  Katsuhiko Ueda ,  Minoru Okamoto ,  Toshihiro Ishikawa ,  Mikako Yasutome

IPC分类号： F02B75/02 ,  G06F12/06 ,  G06F12/00

CPC分类号： G06F12/0607 ,  F02B2075/025

摘要： An interleaving memory system having a first memory device including a 0-bank and a 1-bank for simultaneously outputting data at even-numbered addresses from the 0-bank and data at odd-numbered addresses from the 1-bank, a second memory device including a 0-bank and a 1-bank for simultaneously outputting data at even-numbered addresses from the 0-bank and data at odd-numbered addresses from the 1-bank, and a holding device for holding data from one of the banks of one of the first memory device and the second memory device to delay an output of the data for 1/2 cycle time for sequential addressing. A controller controls first and second selection devices wherein the 0-bank and the 1-bank are alternatively selected when data is outputted either in an ascending order of consecutive addresses from the even-numbered addresses in the first or second memory devices, or in a descending order of consecutive addresses from the odd-numbered addresses in the first or second memory devices. Also, the first holding device and a bank whose output is not held by the first holding device are alternatively selected when data is outputted either in a descending order of consecutive addresses from the even-numbered addresses in the first memory device, or in an ascending order of consecutive addresses from the odd-numbered addresses in the first memory device. The second holding device and a bank whose output is not held by the second holding device are similarly alternatively selected.

摘要翻译： 一种交织存储器系统，具有第一存储器装置，该第一存储器装置包括一个0组和一个一组，用于同时从该第一存储区输出来自0组的偶数地址的数据和奇数地址的数据;第二存储器装置 包括0行和1行，用于从0行同时从偶数行地址输出数据和来自1行的奇数地址的数据;以及保持装置，用于从一个存储体中的一个存储区中保存数据 第一存储器件和第二存储器件之一，用于将数据的输出延迟1/2个周期时间用于顺序寻址。 控制器控制第一和第二选择装置，其中当从第一或第二存储装置中的偶数地址以连续地址的升序输出数据时，交替地选择0组和1组，或者在 来自第一或第二存储器件中的奇数地址的连续地址的降序。 此外，当从第一存储装置中的偶数地址以连续地址的降序输出数据时，交替地选择第一保持装置和输出未被第一保持装置保持的存储体，或者以升序 来自第一存储设备中的奇数地址的连续地址的顺序。 类似地，第二保持装置和输出没有被第二保持装置保持的组。

公开(公告)号：US07551001B2

公开(公告)日：2009-06-23

申请号：US11667302

申请日：2006-10-02

申请人： Tatsuya Tetsukawa ,  Minoru Okamoto ,  Shinichi Marui

发明人： Tatsuya Tetsukawa ,  Minoru Okamoto ,  Shinichi Marui

IPC分类号： H03K19/173

CPC分类号： H03K19/1774 ,  G06F17/5054

摘要： A plurality of logic element groups LEG11 to LEG33 respectively include at least one logic element as a component of a reconfigurable semiconductor integrated circuit. Between any logic element groups engaging in data transmission/reception, e.g., LEG11 and LEG12, clock out terminal and clock in terminal are connected via a line while data out terminal and data in terminal are connected via a delay element 101. The logic element groups LEG11 to LEG33 are therefore independent of one another in terms of timing design. Thus, if redesign is necessary for a semiconductor integrated circuit completed with a plurality of logic element groups, only a new circuit may be designed and connected to an existing circuit, or an unnecessary logic element group may just be removed, to complete a new semiconductor integrated circuit.

摘要翻译： 多个逻辑元件组LEG11至LEG33分别包括作为可重构半导体集成电路的组件的至少一个逻辑元件。 在进行数据发送/接收的任何逻辑元件组（例如LEG11和LEG12）之间，终端中的时钟输出端子和时钟经由线路连接，而数据输出端子和端子中的数据通过延迟元件101连接。逻辑元件组 因此，LEG11至LEG33在时序设计方面彼此独立。 因此，如果对于用多个逻辑元件组完成的半导体集成电路进行重新设计，则可以仅设计新的电路并将其连接到现有的电路，或者可以去除不必要的逻辑元件组以完成新的半导体 集成电路。

公开(公告)号：US07378871B2

公开(公告)日：2008-05-27

申请号：US11264138

申请日：2005-11-02

申请人： Minoru Okamoto

发明人： Minoru Okamoto

IPC分类号： H03K19/173 ,  H03K19/177 ,  H03K19/00

CPC分类号： H03K19/17776 ,  H03K19/1737 ,  H03K19/1776 ,  H03K19/17784

摘要： In a programmable cell included in a first region, configuration information is stored in a volatile memory, while in a programmable cell included in a second region, configuration information is stored in a non-volatile memory. Configuration information for a sub-process common to a plurality of processes is stored in the non-volatile memory.

摘要翻译： 在包括在第一区域中的可编程单元中，配置信息被存储在易失性存储器中，而在包括在第二区域中的可编程单元中，配置信息被存储在非易失性存储器中。 用于多个处理共同的子处理的配置信息存储在非易失性存储器中。

公开(公告)号：US07287149B2

公开(公告)日：2007-10-23

申请号：US11304818

申请日：2005-12-16

申请人： Minoru Okamoto ,  Katsuhiko Ueda

发明人： Minoru Okamoto ,  Katsuhiko Ueda

IPC分类号： G06F9/30 ,  G06F1/32

CPC分类号： G06F9/30196 ,  G06F9/30181

摘要： An information processing method for coding a program to enable an information processing device having an instruction decoder having a reconfigurable circuit, comprises the steps of: simulating execution of the program to obtain a history of instructions executed; extracting a routine in which a number of types of codes used in at least a field among fields constituting an instruction is limited to a predetermined number or less, from the program based on the history; inserting an instruction for changing circuit configuration of the reconfigurable circuit at start and end of the routine; allocating codes so that number of times of change of bit values in a field in which the number of types of codes used are limited is reduced for the routine; and converting a program obtained in the step of inserting an instruction to codes according to the allocation for the routine.

摘要翻译： 一种用于编码程序以使具有具有可重构电路的指令解码器的信息处理装置的信息处理方法包括以下步骤：模拟程序的执行以获得执行的指令的历史; 提取一种程序，其中从构成指令的字段中的至少一个字段中使用的代码数量的数量被限制为预定数量或更少的例程; 在程序的开始和结束时插入用于改变可重新配置电路的电路配置的指令; 分配代码，使得在所使用的代码类型的数量的数量被限制的字段中的比特值的改变次数减少; 以及根据所述例程的分配将在指令插入指令的步骤中获得的程序转换成代码。

公开(公告)号：US07171643B2

公开(公告)日：2007-01-30

申请号：US10787166

申请日：2004-02-27

申请人： Minoru Okamoto

发明人： Minoru Okamoto

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5045

摘要： Adequately assigning features provided by the system to processing units having different architectures incorporated in a system LSI. An analysis unit is provided for counting the number of conditional branch statements and the number of loop control statements, the number of nestings of the conditional branch statements and the number of nestings of the loop control statements, and the number of functions required to generate the conditions of the conditional branch statements and the number of repetitions of loop control statements described in each function of a program describing system features in a high-level language.

摘要翻译： 将由系统提供的特征充分地分配给具有并入系统LSI中的不同架构的处理单元。 提供一个分析单元，用于计数条件分支语句的数量和循环控制语句的数量，条件分支语句的嵌套数量以及循环控制语句的嵌套数量以及生成所需的函数数 条件分支语句的条件以及描述在高级语言中描述系统特征的程序的每个功能中描述的循环控制语句的重复次数。

公开(公告)号：US07139968B2

公开(公告)日：2006-11-21

申请号：US10748242

申请日：2003-12-31

申请人： Ryutaro Yamanaka ,  Hidetoshi Suzuki ,  Hideyuki Kabuo ,  Minoru Okamoto ,  Kevin Mark Stone

发明人： Ryutaro Yamanaka ,  Hidetoshi Suzuki ,  Hideyuki Kabuo ,  Minoru Okamoto ,  Kevin Mark Stone

IPC分类号： H03M13/03

CPC分类号： H03M13/6502 ,  H03M13/3961 ,  H03M13/4107 ,  H03M13/4169 ,  H03M13/6561 ,  H03M13/6563 ,  H03M13/6569

摘要： A digital signal processor configured to perform a Viterbi algorithm includes an instruction fetching unit that fetches instructions and a decoding unit that decodes the instructions fetched by the instruction fetching unit. The digital signal processor also includes an execution unit that executes the instructions decoded by the decoding unit. The execution unit includes an arithmetic logic unit configured to perform a register—register arithmetic logic operation. The arithmetic logic unit compares a first data with a second data, in parallel with a comparison of a third data with a fourth data, and the execution unit outputs new path metrics. Each of the first data, the second data, the third data, and the fourth data is one of four results obtained by adding one of two path metrics to one of two branch metrics.

摘要翻译： 被配置为执行维特比算法的数字信号处理器包括取指令的指令取出单元和对由指令取出单元取出的指令进行解码的解码单元。 数字信号处理器还包括执行由解码单元解码的指令的执行单元。 执行单元包括被配置为执行寄存器寄存器算术逻辑运算的算术逻辑单元。 算术逻辑单元与第三数据与第四数据的比较并行地将第一数据与第二数据进行比较，并且执行单元输出新的路径度量。 第一数据，第二数据，第三数据和第四数据中的每一个是通过将两个路径度量中的一个添加到两个分支度量之一而获得的四个结果之一。

公开(公告)号：US20050204326A1

公开(公告)日：2005-09-15

申请号：US11071465

申请日：2005-03-04

申请人： Kazuhiro Okabayashi ,  Minoru Okamoto

发明人： Kazuhiro Okabayashi ,  Minoru Okamoto

IPC分类号： G06F7/00 ,  G06F15/78 ,  G06F17/50 ,  H01L21/82 ,  H03K19/173

CPC分类号： G06F17/5054

摘要： A method of configuring an information processing system according to the present invention, in an information processing system for realizing one or a plurality of applications, comprises, a step of modeling all of the applications for each certain process level and inputting the models, a step of inputting parameters representing invariability for the inputted models, a step of using the models of the applications and the parameters representing invariability as inputted information and comparing the parameters representing invariability to a boundary condition, and a step of allocating one of the application models to programmable logic and another of the application models to an exclusive-use hardware based on a result of the comparison.

摘要翻译： 一种根据本发明的信息处理系统的配置方法，在用于实现一个或多个应用的​​信息处理系统中，包括：对于每个特定处理级别的所有应用进行建模和输入模型的步骤，步骤 输入表示输入模型的不变性的参数的步骤，使用应用模型和表示不变性的参数作为输入信息并将表示不变性的参数与边界条件进行比较的步骤，以及将应用模型之一分配给可编程 逻辑和另一个应用模型基于比较结果的专用硬件。

公开(公告)号：US06911700B2

公开(公告)日：2005-06-28

申请号：US10664874

申请日：2003-09-22

申请人： Minoru Okamoto

发明人： Minoru Okamoto

IPC分类号： H01L23/12 ,  H01L21/822 ,  H01L23/60 ,  H01L27/04 ,  H01L27/06

CPC分类号： H01L23/60 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/49113 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

摘要： A semiconductor integrated circuit including a digital circuit and an analog circuit which are integrated on a single semiconductor chip comprises a first electrostatic destruction protection circuit, connected to a digital circuit, for protecting the digital circuit from destruction caused by ESD therein by an influence of an input digital signal and a second electrostatic destruction protection circuit, connected to an analog circuit, for protecting the analog circuit from destruction caused by ESD therein by an influence of an input analog signal. A first grounding conductor connected to the first electrostatic destruction protection circuit and a second grounding conductor connected to the second electrostatic destruction protection circuit are connected to each other outside the semiconductor integrated circuit.

摘要翻译： 包括集成在单个半导体芯片上的数字电路和模拟电路的半导体集成电路包括连接到数字电路的第一静电破坏保护电路，用于保护数字电路免受其中的ESD的影响， 输入数字信号和第二静电破坏保护电路，连接到模拟电路，用于通过输入模拟信号的影响来保护模拟电路免受其中的ESD的破坏。 连接到第一静电破坏保护电路的第一接地导体和连接到第二静电破坏保护电路的第二接地导体在半导体集成电路外部彼此连接。

公开(公告)号：US06879193B2

公开(公告)日：2005-04-12

申请号：US10484904

申请日：2002-11-20

申请人： Minoru Okamoto ,  Shinichi Marui ,  Kazuhiro Okabayashi

发明人： Minoru Okamoto ,  Shinichi Marui ,  Kazuhiro Okabayashi

IPC分类号： G06F1/24 ,  H03K17/22 ,  H03L7/00

CPC分类号： G06F1/24

摘要： In a circuit block 110 to be an object of power-off, voltage detecting circuits 130 and 134 are disposed near power supply terminals 140 and 142, respectively, and voltage detecting circuits 132 and 136 are disposed at given positions far from the terminals 140 and 142, respectively, on power lines 141 and 143 of two electric-supply systems. The voltage detecting circuits are each made of MOS transistors only. At turning on the power from a power supply circuit 150 again, after all the voltage detecting circuits have detected arrival of power-supply voltages at a predetermined potential, a reset signal generating circuit 160 stops the input of a reset signal to the circuit block 110. Accordingly, since the reset state is stopped after the arrival of the power-supply voltages at the predetermined voltage, a semiconductor integrated circuit is initialized normally. This provides a semiconductor integrated circuit capable of generating a power-on reset signal appropriately.

摘要翻译： 在作为断电对象的电路块110中，电压检测电路130和134分别设置在电源端子140和142附近，并且电压检测电路132和136设置在远离端子140的给定位置处， 142分别在两个电源系统的电源线141和143上。 电压检测电路仅由MOS晶体管构成。 在再次接通电源电路150的电源时，在所有电压检测电路检测到电源电压达到预定电位之后，复位信号产生电路160停止向电路块110输入复位信号 因此，由于在电源电压到达预定电压之后停止复位状态，因此半导体集成电路被正常初始化。 这提供了能够适当地产生上电复位信号的半导体集成电路。