公开(公告)号：US09269636B2

公开(公告)日：2016-02-23

申请号：US14575490

申请日：2014-12-18

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar ,  Hiroaki Niimi

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/28 ,  H01L27/092

CPC classification number: H01L21/823857 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28202 ,  H01L21/28238 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/82385 ,  H01L27/0922 ,  H01L29/66545 ,  H01L29/6659

Abstract: A replacement metal gate transistor is formed with high quality gate dielectric under the high-k dielectric. The high quality gate dielectric is formed on the substrate at a temperature of at least 850° C. A sacrificial gate dielectric is formed on the high quality gate dielectric and a polysilicon replacement gate is formed on the sacrificial gate dielectric. The polysilicon replacement gate is removed leaving a gate trench. The sacrificial gate dielectric is removed from a bottom of the gate. A high-k dielectric is deposited into the gate trench. Metal gate material is deposited on the high-k dielectric.

Abstract translation: 在高k电介质下形成具有高质量栅极电介质的替代金属栅极晶体管。 在至少850℃的温度下在衬底上形成高质量的栅极电介质。在高质量栅极电介质上形成牺牲栅极电介质，并且在牺牲栅极电介质上形成多晶硅替代栅极。 去除多晶硅替代栅极留下栅极沟槽。 从栅极的底部去除牺牲栅极电介质。 高k电介质沉积到栅极沟槽中。 金属栅极材料沉积在高k电介质上。

公开(公告)号：US20150287643A1

公开(公告)日：2015-10-08

申请号：US14724185

申请日：2015-05-28

Applicant: Texas Instruments Incorporated

Inventor： Hiroaki Niimi ,  Brian K. Kirkpatrick

IPC: H01L21/8238 ,  H01L21/3213 ,  H01L21/477 ,  H01L21/28

CPC classification number: H01L21/82385 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/32131 ,  H01L21/32133 ,  H01L21/32134 ,  H01L21/324 ,  H01L21/477 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: An integrated circuit with a thick TiN metal gate with a work function greater than 4.85 eV and with a thin TiN metal gate with a work function less than 4.25 eV. An integrated circuit with a replacement gate PMOS TiN metal gate transistor with a workfunction greater than 4.85 eV and with a replacement gate NMOS TiN metal gate transistor with a workfunction less than 4.25 eV. An integrated circuit with a gate first PMOS TiN metal gate transistor with a workfunction greater than 4.85 eV and with a gate first NMOS TiN metal gate transistor with a workfunction less than 4.25 eV.

Abstract translation: 具有厚度大于4.85eV的功函数的厚TiN金属栅的集成电路，并具有工作功能小于4.25eV的薄TiN金属栅。 具有替代栅极PMOS TiN金属栅极晶体管的集成电路，其功函数大于4.85eV，并具有功函数小于4.25eV的替代栅极NMOS TiN金属栅极晶体管。 具有栅极第一PMOS TiN金属栅极晶体管的集成电路，其功函数大于4.85eV，并具有功函数小于4.25eV的栅极第一NMOS TiN金属栅极晶体管。

公开(公告)号：US20150187771A1

公开(公告)日：2015-07-02

申请号：US14578732

申请日：2014-12-22

Applicant: Texas Instruments Incorporated

Inventor： Hiroaki Niimi ,  Manoj Mehrotra ,  Mahalingam Nandakumar

IPC: H01L27/092 ,  H01L29/49 ,  H01L29/423 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/8238 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/28 ,  H01L21/321 ,  H01L29/51 ,  H01L21/027

CPC classification number: H01L27/092 ,  H01L21/02148 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/0271 ,  H01L21/0273 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28158 ,  H01L21/28202 ,  H01L21/28238 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/3212 ,  H01L21/32133 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

Abstract: An integrated circuit and method with a metal gate NMOS transistor with a high-k first gate dielectric on a high quality thermally grown interface dielectric and with a metal gate PMOS transistor with a high-k last gate dielectric on a chemically grown interface dielectric.

Abstract translation: 一种具有金属栅极NMOS晶体管的集成电路和方法，其在高质量热生长界面电介质上具有高k第一栅极电介质，并且具有在化学生长界面电介质上具有高k最后栅极电介质的金属栅极PMOS晶体管。

公开(公告)号：US09000539B2

公开(公告)日：2015-04-07

申请号：US13671730

申请日：2012-11-08

Applicant: Texas Instruments Incorporated

Inventor： Manoj Mehrotra ,  Hiroaki Niimi

IPC: H01L29/76 ,  H01L29/94 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/78 ,  H01L21/28114 ,  H01L29/0653 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

Abstract: The gate-to-source and gate-to-drain overlap capacitance of a MOS transistor with a metal gate and a high-k gate dielectric are reduced by forming the high-k gate dielectric along the inside of a sidewall structure which has been formed to lie further away from the source and the drain.

Abstract translation: 通过沿着形成的侧壁结构的内部形成高k栅极电介质来减小具有金属栅极和高k栅极电介质的MOS晶体管的栅极到源极和栅极到漏极的重叠电容 远离源头和排水沟。

公开(公告)号：US20140342521A1

公开(公告)日：2014-11-20

申请号：US14451485

申请日：2014-08-05

Applicant: Texas Instruments Incorporated

Inventor： Hiroaki Niimi ,  Jarvis Benjamin Jacobs ,  Ajith Varghese

IPC: H01L21/324 ,  H01L21/265 ,  H01L29/66

CPC classification number: H01L21/324 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/823412 ,  H01L21/823462 ,  H01L29/105 ,  H01L29/66477

Abstract: A two-step thermal treatment method consists of performing ion implantation in a silicon substrate of the semiconductor device. A first thermal treatment procedure is performed on the semiconductor device. A second thermal treatment procedure is consecutively performed on the semiconductor device to reduce damage produced by the ion implantation.

Abstract translation: 两步热处理方法包括在半导体器件的硅衬底中进行离子注入。 在半导体器件上执行第一热处理程序。 在半导体器件上连续执行第二热处理程序以减少由离子注入产生的损伤。

公开(公告)号：US20140183653A1

公开(公告)日：2014-07-03

申请号：US14142323

申请日：2013-12-27

Applicant: Texas Instruments Incorporated

Inventor： Hiroaki Niimi ,  James Joseph Chambers

IPC: H01L29/51 ,  H01L27/092 ,  H01L21/28

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7833

Abstract: An integrated circuit containing metal replacement gates may be formed by forming a nitrogen-rich titanium-based barrier between a high-k gate dielectric layer and a metal work function layer of a PMOS transistor. The nitrogen-rich titanium-based barrier is less than 1 nanometer thick and has an atomic ratio of titanium to nitrogen of less than 43:57. The nitrogen-rich titanium-based barrier may be formed by forming a titanium based layer over the gate dielectric layer and subsequently adding nitrogen to the titanium based layer. The metal work function layer is formed over the nitrogen-rich titanium-based barrier.

Abstract translation: 可以通过在高k栅介质层和PMOS晶体管的金属功函数层之间形成富氮钛基阻挡层来形成包含金属替换栅的集成电路。 富氮钛基阻挡层小于1纳米厚，钛与氮的原子比小于43:57。 可以通过在栅极电介质层上形成钛基层并随后将氮添加到钛基层来形成富氮钛基阻挡层。 在富氮钛基屏障上形成金属功函数层。

公开(公告)号：US20130337656A1

公开(公告)日：2013-12-19

申请号：US13968074

申请日：2013-08-15

Applicant: Texas Instruments Incorporated

Inventor： James Joseph Chambers ,  Hiroaki Niimi

IPC: H01L21/283

CPC classification number: H01L21/283 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

Abstract: A CMOS device having an NMOS transistor with a metal gate electrode comprising a mid-gap metal with a low work function/high oxygen affinity cap and a PMOS transistor with a metal gate electrode comprising a mid gap metal with a high work function/low oxygen affinity cap and method of forming.

Abstract translation: 一种具有NMOS晶体管的CMOS器件，其具有包括具有低功函数/高氧亲和性帽的中间间隙金属的金属栅极和具有金属栅电极的PMOS晶体管，该金属栅电极包括具有高功函数/低氧的中间间隙金属 亲和帽和成型方法。

公开(公告)号：US10163725B2

公开(公告)日：2018-12-25

申请号：US15292373

申请日：2016-10-13

Applicant: Texas Instruments Incorporated

Inventor： Manoj Mehrotra ,  Charles Frank Machala, III ,  Rick L. Wise ,  Hiroaki Niimi

IPC: H01L21/02 ,  H01L21/70 ,  H01L21/8238 ,  H01L21/20 ,  H01L21/36 ,  H01L27/092 ,  H01L27/11 ,  H01L29/10 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20

Abstract: An integrated circuit containing an n-channel finFET and a p-channel finFET is formed by forming a first polarity fin epitaxial layer for a first polarity finFET, and subsequently forming a hard mask which exposes an area for a second, opposite, polarity fin epitaxial layer for a second polarity finFET. The second polarity fin epitaxial layer is formed in the area exposed by the hard mask. A fin mask defines the first polarity fin and second polarity fin areas, and a subsequent fin etch forms the respective fins. A layer of isolation dielectric material is formed over the substrate and fins. The layer of isolation dielectric material is planarized down to the fins. The layer of isolation dielectric material is recessed so that the fins extend at least 10 nanometers above the layer of isolation dielectric material. Gate dielectric layers and gates are formed over the fins.

公开(公告)号：US10068771B2

公开(公告)日：2018-09-04

申请号：US15865758

申请日：2018-01-09

Applicant: Texas Instruments Incorporated

Inventor： Malcolm J. Bevan ,  Haowen Bu ,  Hiroaki Niimi ,  Husam N. Alshareef

IPC: H01L21/00 ,  H01J37/00 ,  H01L21/28 ,  C23C16/455 ,  C23C16/458 ,  H01J37/32 ,  H01L21/02 ,  H01L29/51

Abstract: Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in oxide growth can be achieved by maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth of the gate dielectric layer between at least two sequential process steps used in the fabrication the gate dielectric structure. Maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth also improves the uniformity of nitrogen implanted in the gate dielectric.

公开(公告)号：US09960162B2

公开(公告)日：2018-05-01

申请号：US15184405

申请日：2016-06-16

Applicant: Texas Instruments Incorporated

Inventor： Hiroaki Niimi ,  Manoj Mehrotra ,  Mahalingam Nandakumar

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/027 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L27/092 ,  H01L21/02148 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/0271 ,  H01L21/0273 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28158 ,  H01L21/28202 ,  H01L21/28238 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/3212 ,  H01L21/32133 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

Abstract: An integrated circuit and method with a metal gate NMOS transistor with a high-k first gate dielectric on a high quality thermally grown interface dielectric and with a metal gate PMOS transistor with a high-k last gate dielectric on a chemically grown interface dielectric.