公开(公告)号：US20200371962A1

公开(公告)日：2020-11-26

申请号：US16882374

申请日：2020-05-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen BHORIA ,  Timothy David ANDERSON ,  Pete HIPPLEHEUSER

IPC: G06F12/128 ,  G06F12/0811

Abstract: A caching system including a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes: line type bits configured to store an indication that a corresponding cache line of the second sub-cache is configured to store write-miss data, and an eviction controller configured to evict a cache line of the second sub-cache storing write-miss data based on an indication that the cache line has been fully written.

公开(公告)号：US20200371928A1

公开(公告)日：2020-11-26

申请号：US16882390

申请日：2020-05-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen BHORIA ,  Timothy David ANDERSON ,  Pete HIPPLEHEUSER

IPC: G06F12/0811 ,  G06F12/0891 ,  G06F12/0884 ,  G06F12/02

Abstract: A caching system including a first sub-cache, a second sub-cache, coupled in parallel with the first sub-cache, for storing write-memory commands that are not cached in the first sub-cache, the second sub-cache including privilege bits configured to store an indication that a corresponding cache line of the second sub-cache is associated with a level of privilege, and wherein the second sub-cache is further configured to receive a first write memory command for a memory address associated with a first level of privilege, store, in the second sub-cache, first data associated with the first write memory command and the level of privilege associated with the cache line, receive a second write memory command for the cache line, the second write memory command associated with a second level of privilege, merge the first level of privilege with the second level of privilege, and output the merged privilege level with the cache line.

公开(公告)号：US20200371803A1

公开(公告)日：2020-11-26

申请号：US16421920

申请日：2019-05-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Timothy David ANDERSON ,  Duc Quang BUI ,  Joseph ZBICIAK ,  Kai CHIRCA

IPC: G06F9/30

Abstract: A digital signal processor having a CPU with a program counter register and, optionally, an event context stack pointer register for saving and restoring the event handler context when higher priority event preempts a lower priority event handler. The CPU is configured to use a minimized set of addressing modes that includes using the event context stack pointer register and program counter register to compute an address for storing data in memory. The CPU may also eliminate post-decrement, pre-increment and post-decrement addressing and rely only on post-increment addressing.

公开(公告)号：US20200371790A1

公开(公告)日：2020-11-26

申请号：US16786457

申请日：2020-02-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Duc Quang BUI ,  Alan L. DAVIS ,  Dheera Balasubramanian SAMUDRALA ,  Timothy David ANDERSON

IPC: G06F9/30 ,  G06F9/38

Abstract: A method of storing register data elements to interleave with data elements of a different register, a processor thereof, and a system thereof, wherein each non-consecutive data elements of a register is retrieved to be stored to interleave with each non-consecutive data elements of a different register upon an executive of an interleaving store instruction, wherein a mask instruction directing a lane of a storage space in which the non-consecutive data elements are stored is executed in conjunction with the interleaving store instruction, and wherein a processor of a second type is configured to emulate a processor of a first type to store the non-consecutive data elements the same as non-consecutive data elements stored in the first type processor.

公开(公告)号：US20250028652A1

公开(公告)日：2025-01-23

申请号：US18909000

申请日：2024-10-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen BHORIA ,  Timothy David ANDERSON ,  Pete HIPPLEHEUSER

IPC: G06F12/128 ,  G06F9/30 ,  G06F9/54 ,  G06F11/10 ,  G06F12/02 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/0853 ,  G06F12/0855 ,  G06F12/0864 ,  G06F12/0884 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/12 ,  G06F12/121 ,  G06F12/126 ,  G06F12/127 ,  G06F13/16 ,  G06F15/80 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C29/42 ,  G11C29/44

Abstract: A caching system including a first sub-cache, and a second sub-cache coupled in parallel with the first sub-cache; wherein the second sub-cache includes line type bits configured to store an indication that a corresponding line of the second sub-cache is configured to store write-miss data.

公开(公告)号：US20240104026A1

公开(公告)日：2024-03-28

申请号：US18535162

申请日：2023-12-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen BHORIA ,  Timothy David ANDERSON ,  Pete HIPPLEHEUSER

IPC: G06F12/128 ,  G06F9/30 ,  G06F9/54 ,  G06F11/10 ,  G06F12/02 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/0853 ,  G06F12/0855 ,  G06F12/0864 ,  G06F12/0884 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/12 ,  G06F12/121 ,  G06F12/126 ,  G06F12/127 ,  G06F13/16 ,  G06F15/80 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C29/42 ,  G11C29/44

CPC classification number: G06F12/128 ,  G06F9/3001 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/546 ,  G06F11/1064 ,  G06F12/0215 ,  G06F12/0238 ,  G06F12/0292 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/082 ,  G06F12/0853 ,  G06F12/0855 ,  G06F12/0864 ,  G06F12/0884 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/12 ,  G06F12/121 ,  G06F12/126 ,  G06F12/127 ,  G06F13/1605 ,  G06F13/1642 ,  G06F13/1673 ,  G06F13/1689 ,  G06F15/8069 ,  G11C5/066 ,  G11C7/10 ,  G11C7/1015 ,  G11C7/106 ,  G11C7/1075 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/222 ,  G11C29/42 ,  G11C29/44 ,  G06F2212/1016 ,  G06F2212/1021 ,  G06F2212/1024 ,  G06F2212/1041 ,  G06F2212/1044 ,  G06F2212/301 ,  G06F2212/454 ,  G06F2212/6032 ,  G06F2212/6042 ,  G06F2212/608 ,  G06F2212/62

Abstract: A caching system including a first sub-cache, and a second sub-cache, coupled in parallel with the first cache, for storing cache data evicted from the first sub-cache and write-memory commands that are not cached in the first sub-cache, and wherein the second sub-cache includes: color tag bits configured to store an indication that a corresponding cache line of the second sub-cache storing write miss data is associated with a color tag, and an eviction controller configured to evict cache lines of the second sub-cache storing write-miss data based on the color tag associated with the cache line.

公开(公告)号：US20240078190A1

公开(公告)日：2024-03-07

申请号：US18497005

申请日：2023-10-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen BHORIA ,  Timothy David ANDERSON ,  Pete HIPPLEHEUSER

IPC: G06F12/128 ,  G06F9/30 ,  G06F9/54 ,  G06F11/10 ,  G06F12/02 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/0853 ,  G06F12/0855 ,  G06F12/0864 ,  G06F12/0884 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/12 ,  G06F12/121 ,  G06F12/126 ,  G06F12/127 ,  G06F13/16 ,  G06F15/80 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22 ,  G11C29/42 ,  G11C29/44

CPC classification number: G06F12/128 ,  G06F9/3001 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/546 ,  G06F11/1064 ,  G06F12/0215 ,  G06F12/0238 ,  G06F12/0292 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/082 ,  G06F12/0853 ,  G06F12/0855 ,  G06F12/0864 ,  G06F12/0884 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/12 ,  G06F12/121 ,  G06F12/126 ,  G06F12/127 ,  G06F13/1605 ,  G06F13/1642 ,  G06F13/1673 ,  G06F13/1689 ,  G06F15/8069 ,  G11C5/066 ,  G11C7/10 ,  G11C7/1015 ,  G11C7/106 ,  G11C7/1075 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/222 ,  G11C29/42 ,  G11C29/44 ,  G06F2212/1016 ,  G06F2212/1021 ,  G06F2212/1024 ,  G06F2212/1041 ,  G06F2212/1044 ,  G06F2212/301 ,  G06F2212/454 ,  G06F2212/6032 ,  G06F2212/6042 ,  G06F2212/608 ,  G06F2212/62

Abstract: A caching system including a first sub-cache, a second sub-cache, coupled in parallel with the first sub-cache, for storing write-memory commands that are not cached in the first sub-cache, the second sub-cache including privilege bits configured to store an indication that a corresponding cache line of the second sub-cache is associated with a level of privilege, and wherein the second sub-cache is further configured to receive a first write memory command for a memory address associated with a first level of privilege, store, in the second sub-cache, first data associated with the first write memory command and the level of privilege associated with the cache line, receive a second write memory command for the cache line, the second write memory command associated with a second level of privilege, merge the first level of privilege with the second level of privilege, and output the merged privilege level with the cache line.

公开(公告)号：US20240004800A1

公开(公告)日：2024-01-04

申请号：US18469825

申请日：2023-09-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Naveen BHORIA ,  Timothy David ANDERSON ,  Pete HIPPLEHEUSER

IPC: G06F12/128 ,  G06F12/0888 ,  G06F12/0891 ,  G06F9/54 ,  G06F12/02 ,  G06F12/0811 ,  G06F12/0817 ,  G06F12/0804 ,  G06F9/30 ,  G11C7/10 ,  G11C29/42 ,  G11C29/44 ,  G06F11/10 ,  G06F12/0855 ,  G06F12/12 ,  G06F12/0806 ,  G06F12/0815 ,  G06F12/0853 ,  G06F13/16 ,  G06F12/121 ,  G06F12/0884 ,  G06F12/0897 ,  G06F12/0895 ,  G06F12/0864 ,  G11C7/22 ,  G11C5/06 ,  G06F15/80 ,  G06F12/0802 ,  G06F12/126 ,  G06F12/127

CPC classification number: G06F12/128 ,  G06F12/0888 ,  G06F12/0891 ,  G06F9/546 ,  G06F12/0215 ,  G06F12/0238 ,  G06F12/0811 ,  G06F12/082 ,  G06F12/0804 ,  G06F9/3001 ,  G06F9/30047 ,  G11C7/106 ,  G11C7/1087 ,  G11C29/42 ,  G11C29/44 ,  G06F11/1064 ,  G06F12/0855 ,  G06F12/12 ,  G06F12/0806 ,  G06F12/0815 ,  G06F12/0853 ,  G06F13/1605 ,  G06F12/121 ,  G06F12/0292 ,  G06F12/0884 ,  G06F12/0897 ,  G06F12/0895 ,  G06F12/0864 ,  G11C7/222 ,  G11C7/1075 ,  G11C7/1078 ,  G06F13/1642 ,  G06F13/1673 ,  G06F13/1689 ,  G11C5/066 ,  G11C7/10 ,  G11C7/1015 ,  G06F15/8069 ,  G06F12/0802 ,  G06F9/30043 ,  G06F12/126 ,  G06F12/127 ,  G06F2212/1021 ,  G06F2212/608 ,  G06F2212/6032 ,  G06F2212/1024 ,  G06F2212/62 ,  G06F2212/1016 ,  G06F2212/1041 ,  G06F2212/1044 ,  G06F2212/301 ,  G06F2212/454 ,  G06F2212/6042

Abstract: Techniques for caching data are provided that include receiving, by a caching system, a write memory command for a memory address, the write memory command associated with a first color tag, determining, by a first sub-cache of the caching system, that the memory address is not cached in the first sub-cache, determining, by second sub-cache of the caching system, that the memory address is not cached in the second sub-cache, storing first data associated with the first write memory command in a cache line of the second sub-cache, storing the first color tag in the second sub-cache, receiving a second write memory command for the cache line, the write memory command associated with a second color tag, merging the second color tag with the first color tag, storing the merged color tag, and evicting the cache line based on the merged color tag.

公开(公告)号：US20230297506A1

公开(公告)日：2023-09-21

申请号：US18325190

申请日：2023-05-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok CHACHAD ,  David Matthew THOMPSON ,  Timothy David ANDERSON ,  Kai CHIRCA

IPC: G06F12/0811 ,  G06F12/0815 ,  G06F12/128 ,  G06F12/0817 ,  G06F12/084 ,  G06F9/30 ,  G06F11/30 ,  G06F12/0808 ,  G06F13/16 ,  G06F9/38 ,  G06F9/46 ,  G06F9/54 ,  G06F12/0895 ,  G06F12/0831

CPC classification number: G06F12/0811 ,  G06F12/0815 ,  G06F12/128 ,  G06F12/0828 ,  G06F12/084 ,  G06F9/30047 ,  G06F9/30079 ,  G06F11/3037 ,  G06F12/0808 ,  G06F13/1668 ,  G06F9/3867 ,  G06F9/467 ,  G06F9/544 ,  G06F9/546 ,  G06F12/0895 ,  G06F12/0831 ,  G06F2212/608 ,  G06F2212/1021

Abstract: A method includes receiving, by a level two (L2) controller, a first request for a cache line in a shared cache coherence state; mapping, by the L2 controller, the first request to a second request for a cache line in an exclusive cache coherence state; and responding, by the L2 controller, to the second request.

公开(公告)号：US20230058689A1

公开(公告)日：2023-02-23

申请号：US17981591

申请日：2022-11-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok CHACHAD ,  Timothy David ANDERSON ,  David Matthew THOMPSON

IPC: G06F9/46 ,  G06F9/48 ,  G06F9/448 ,  G06F11/30 ,  G06F9/54 ,  G06F12/0811 ,  G06F9/38 ,  G06F12/0813 ,  G06F12/0817 ,  G06F9/30 ,  G06F12/0871 ,  G06F12/0891 ,  G06F12/12 ,  G06F13/16 ,  G06F12/0888 ,  G06F12/0831 ,  G06F12/0855

Abstract: An apparatus includes a CPU core, a first cache subsystem coupled to the CPU core, and a second memory coupled to the cache subsystem. The first cache subsystem includes a configuration register, a first memory, and a controller. The controller is configured to: receive a request directed to an address in the second memory and, in response to the configuration register having a first value, operate in a non-caching mode. In the non-caching mode, the controller is configured to provide the request to the second memory without caching data returned by the request in the first memory. In response to the configuration register having a second value, the controller is configured to operate in a caching mode. In the caching mode the controller is configured to provide the request to the second memory and cache data returned by the request in the first memory.