公开(公告)号：US10510693B2

公开(公告)日：2019-12-17

申请号：US15717940

申请日：2017-09-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Chiang Wu ,  Chun-Lin Lu ,  Chao-Wen Shih ,  Han-Ping Pu ,  Nan-Chin Chuang

IPC: H01L23/66 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01Q21/06 ,  H01Q1/22 ,  H01L23/31

Abstract: A semiconductor package structure including an encapsulation body, an RFIC chip, a first antenna structure, and a second antenna structure is provided. The RFIC chip may be embedded in the encapsulation body. The first antenna structure may be disposed at a lateral side of the RFIC chip, electrically connected to the RFIC chip, and include a first conductor layer and a plurality of first patches opposite to the first conductor layer. The second antenna structure may be stacked on the RFIC chip, electrically connected to the RFIC chip, and include a second conductor layer and a plurality of second patches opposite to the second conductor layer. The first patches and the second patches are located at a surface of the encapsulation body. A first distance between the first conductor layer and the first patches is different from a second distance between the second conductor layer and the second patches.

公开(公告)号：US10381309B2

公开(公告)日：2019-08-13

申请号：US15965980

申请日：2018-04-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chuei-Tang Wang ,  Chung-Hao Tsai ,  Chen-Hua Yu ,  Chun-Lin Lu ,  Chao-Wen Shih ,  Han-Ping Pu ,  Kai-Chiang Wu ,  Albert Wan

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/28 ,  H01L25/065 ,  H01L25/00

Abstract: A package structure includes a first redistribution layer, a second redistribution layer, at least one semiconductor chip, an insulating encapsulation, a protection layer, and at least one connecting module. The at least one semiconductor chip is located between and electrically connected to the first redistribution layer and the second redistribution layer. The insulating encapsulation encapsulates the at least one semiconductor chip. The protection layer is disposed on and partially covers the first redistribution layer, wherein the first redistribution layer is located between the at least one semiconductor chip and the protection layer. The at least one connecting module connects to the first redistribution layer and is electrically connected to the at least one semiconductor chip through the first redistribution layer, wherein the at least one connecting module comprises a plurality of pins, and the at least one connecting module is mounted onto the first redistribution layer by the protection layer and is accessibly exposed by the protection layer.

公开(公告)号：US09559071B2

公开(公告)日：2017-01-31

申请号：US13927972

申请日：2013-06-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Chun-Lin Lu ,  Kai-Chiang Wu ,  Ming-Kai Liu ,  Yen-Ping Wang ,  Shih-Wei Liang ,  Ching-Feng Yang ,  Chia-Chun Miao ,  Hung-Jen Lin

IPC: H01L29/24 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L24/81 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03472 ,  H01L2224/03828 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/0554 ,  H01L2224/05559 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/11015 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/1181 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/1308 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/1319 ,  H01L2224/14051 ,  H01L2224/14131 ,  H01L2224/14135 ,  H01L2224/14179 ,  H01L2224/14505 ,  H01L2224/1601 ,  H01L2224/16057 ,  H01L2224/16058 ,  H01L2224/16238 ,  H01L2224/17051 ,  H01L2224/17517 ,  H01L2224/81011 ,  H01L2224/81024 ,  H01L2224/81148 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/814 ,  H01L2224/81815 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/207 ,  H01L2924/014 ,  H01L2924/00012

Abstract: Embodiments of mechanisms for forming a package structure are provided. The package structure includes a semiconductor die and a substrate. The package structure includes a pillar bump and an elongated solder bump bonded to the semiconductor die and the substrate. A height of the elongated solder bump is substantially equal to a height of the pillar bump. The elongated solder bump has a first width, at a first horizontal plane passing through an upper end of a sidewall surface of the elongated solder bump, and a second width, at a second horizontal plane passing through a midpoint of the sidewall surface. A ratio of the second width to the first width is in a range from about 0.5 to about 1.1.

Abstract translation: 提供了用于形成封装结构的机构的实施例。 封装结构包括半导体管芯和衬底。 封装结构包括柱状凸起和与半导体管芯和衬底结合的细长焊料凸块。 细长焊料凸块的高度基本上等于柱形凸块的高度。 细长的焊料凸块在通过细长焊料凸块的侧壁表面的上端的第一水平面处具有第一宽度，并且在通过侧壁表面的中点的第二水平面处具有第二宽度。 第二宽度与第一宽度的比率在约0.5至约1.1的范围内。