公开(公告)号：US20230253280A1

公开(公告)日：2023-08-10

申请号：US18194876

申请日：2023-04-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Yu-Wei Chen ,  Li-Chung Kuo ,  Ying-Ching Shih ,  Szu-Wei Lu ,  Jing-Cheng Lin ,  Long Hua Lee ,  Kuan-Yu Huang

IPC: H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/3135 ,  H01L23/3128 ,  H01L23/49816 ,  H01L21/563 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2225/0651 ,  H01L2225/0652

Abstract: A method for forming an underfill structure and semiconductor packages including the underfill structure are disclosed. In an embodiment, the semiconductor package may include a package including an integrated circuit die; an interposer bonded to the integrated circuit die by a plurality of die connectors; and an encapsulant surrounding the integrated circuit die. The semiconductor package may further include a package substrate bonded to the interposer by a plurality of conductive connectors; a first underfill between the package and the package substrate, the first underfill having a first coefficient of thermal expansion (CTE); and a second underfill surrounding the first underfill, the second underfill having a second CTE less than the first CTE.

公开(公告)号：US11688728B2

公开(公告)日：2023-06-27

申请号：US17382565

申请日：2021-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Cheng Lin ,  Jui-Pin Hung ,  Hsien-Wen Liu ,  Min-Chen Lin

IPC: H01L25/00 ,  H01L23/525 ,  H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/532 ,  H01L23/538 ,  H01L21/56

CPC classification number: H01L25/50 ,  H01L21/56 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/49811 ,  H01L23/525 ,  H01L23/5329 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/19 ,  H01L24/81 ,  H01L25/065 ,  H01L21/568 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05027 ,  H01L2224/05166 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/11013 ,  H01L2224/1134 ,  H01L2224/1148 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/96 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/96 ,  H01L2224/03 ,  H01L2224/96 ,  H01L2224/11 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/05166 ,  H01L2924/00014 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2224/13147 ,  H01L2924/00014

Abstract: An embodiment integrated circuit structure includes a substrate, a metal pad over the substrate, a post-passivation interconnect (PPI) structure over the substrate and electronically connected to the metal pad, a first polymer layer over the PPI structure, an under bump metallurgy (UBM) extending into an opening in the first polymer layer and electronically connected to the PPI structure, and a barrier layer on a top surface of the first polymer layer adjacent to the UBM.

公开(公告)号：US11646220B2

公开(公告)日：2023-05-09

申请号：US17650926

申请日：2022-02-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  An-Jhih Su ,  Chi-Hsi Wu ,  Der-Chyang Yeh ,  Ming Shih Yeh ,  Jing-Cheng Lin ,  Hung-Jui Kuo

IPC: H01L21/768 ,  H01L21/48 ,  H01L23/48 ,  H01L23/498 ,  H01L23/522 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L21/76805 ,  H01L21/486 ,  H01L21/4853 ,  H01L21/76813 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/5384 ,  H01L24/24 ,  H01L24/27 ,  H01L24/28 ,  H01L24/73 ,  H01L24/82 ,  H01L24/13 ,  H01L24/32 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/244 ,  H01L2224/24147 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/32145 ,  H01L2224/32265 ,  H01L2224/73215 ,  H01L2224/73217 ,  H01L2224/73227 ,  H01L2224/73267 ,  H01L2224/821 ,  H01L2224/82051 ,  H01L2224/82951 ,  H01L2224/83191 ,  H01L2224/83815 ,  H01L2224/83895

Abstract: A method includes forming a metal layer extending into openings of a dielectric layer to contact a first metal pad and a second metal pad, and bonding a bottom terminal of a component device to the metal layer. The metal layer has a first portion directly underlying and bonded to the component device. A raised via is formed on the metal layer, and the metal layer has a second portion directly underlying the raised via. The metal layer is etched to separate the first portion and the second portion of the metal layer from each other. The method further includes coating the raised via and the component device in a dielectric layer, revealing the raised via and a top terminal of the component device, and forming a redistribution line connecting the raised via to the top terminal.

公开(公告)号：US11527418B2

公开(公告)日：2022-12-13

申请号：US17026712

申请日：2020-09-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Cheng Lin ,  Li-Hui Cheng ,  Po-Hao Tsai

IPC: H01L21/56 ,  H01L21/78 ,  H01L23/31 ,  H01L21/683 ,  H01L23/00 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L21/66

Abstract: An integrated circuit package and a method of forming the same are provided. A method includes forming a conductive column over a carrier. An integrated circuit die is attached to the carrier, the integrated circuit die being disposed adjacent the conductive column. An encapsulant is formed around the conductive column and the integrated circuit die. The carrier is removed to expose a first surface of the conductive column and a second surface of the encapsulant. A polymer material is formed over the first surface and the second surface. The polymer material is cured to form an annular-shaped structure. An inner edge of the annular-shaped structure overlaps the first surface in a plan view. An outer edge of the annular-shaped structure overlaps the second surface in the plan view.

公开(公告)号：US20220328421A1

公开(公告)日：2022-10-13

申请号：US17853593

申请日：2022-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Cheng Lin ,  Chen-Hua Yu ,  Po-Hao Tsai

IPC: H01L23/544 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor device has a conductive via laterally separated from the semiconductor, an encapsulant between the semiconductor device and the conductive via, and a mark. The mark is formed from characters that are either cross-free characters or else have a overlap count of less than two. In another embodiment the mark is formed using a wobble scan methodology. By forming marks as described, defects from the marking process may be reduced or eliminated.

公开(公告)号：US20220199465A1

公开(公告)日：2022-06-23

申请号：US17676627

申请日：2022-02-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Wu ,  Ying-Ching Shih ,  Szu-Wei Lu ,  Jing-Cheng Lin ,  Long Hua Lee

IPC: H01L21/768 ,  H01L21/56 ,  H01L23/31 ,  H01L23/367 ,  H01L23/00

Abstract: A method of forming a semiconductor device includes attaching a metal foil to a carrier, the metal foil being pre-made prior to attaching the metal foil; forming a conductive pillar on a first side of the metal foil distal the carrier; attaching a semiconductor die to the first side of the metal foil; forming a molding material around the semiconductor die and the conductive pillar; and forming a redistribution structure over the molding material.

公开(公告)号：US11201135B2

公开(公告)日：2021-12-14

申请号：US15299961

申请日：2016-10-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Cheng Lin ,  Shang-Yun Hou

IPC: H01L23/13 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L25/00 ,  H01L23/498 ,  H01L21/683 ,  H01L21/60

Abstract: A semiconductor package and a method of forming a semiconductor package with one or more dies over an interposer are provided. In some embodiments, the semiconductor package has a plurality of through substrate vias (TSVs) extending through an interposer substrate. A redistribution structure is arranged over a first surface of the interposer substrate, and a first die is bonded to the redistribution structure. An edge of the first die is beyond a nearest edge of the interposer substrate. A second die is bonded to the redistribution structure. The second die is laterally separated from the first die by a space.

公开(公告)号：US20210358825A1

公开(公告)日：2021-11-18

申请号：US17384923

申请日：2021-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Wei Chen ,  Li-Chung Kuo ,  Ying-Ching Shih ,  Szu-Wei Lu ,  Jing-Cheng Lin ,  Long Hua Lee ,  Kuan-Yu Huang

IPC: H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065

Abstract: A method for forming an underfill structure and semiconductor packages including the underfill structure are disclosed. In an embodiment, the semiconductor package may include a package including an integrated circuit die; an interposer bonded to the integrated circuit die by a plurality of die connectors; and an encapsulant surrounding the integrated circuit die. The semiconductor package may further include a package substrate bonded to the interposer by a plurality of conductive connectors; a first underfill between the package and the package substrate, the first underfill having a first coefficient of thermal expansion (CTE); and a second underfill surrounding the first underfill, the second underfill having a second CTE less than the first CTE.

公开(公告)号：US20210335701A1

公开(公告)日：2021-10-28

申请号：US17372747

申请日：2021-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Cheng Lin ,  Chi-Hsi Wu ,  Chen-Hua Yu ,  Po-Hao Tsai

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L25/065

Abstract: A semiconductor device includes a substrate, a first redistribution layer (RDL) over a first side of the substrate, one or more semiconductor dies over and electrically coupled to the first RDL, and an encapsulant over the first RDL and around the one or more semiconductor dies. The semiconductor device also includes connectors attached to a second side of the substrate opposing the first side, the connectors being electrically coupled to the first RDL. The semiconductor device further includes a polymer layer on the second side of the substrate, the connectors protruding from the polymer layer above a first surface of the polymer layer distal the substrate. A first portion of the polymer layer contacting the connectors has a first thickness, and a second portion of the polymer layer between adjacent connectors has a second thickness smaller than the first thickness.

公开(公告)号：US20210287957A1

公开(公告)日：2021-09-16

申请号：US17335588

申请日：2021-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jing-Cheng Lin ,  Shih-Yi Syu

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/48 ,  H01L25/065 ,  H01L21/48 ,  H01L21/768 ,  H01L25/075

Abstract: A die includes a semiconductor substrate, a through-via penetrating through the semiconductor substrate, a seal ring overlying and connected to the through-via, and an electrical connector underlying the semiconductor substrate and electrically coupled to the seal ring through the through-via.