公开(公告)号：US11626328B2

公开(公告)日：2023-04-11

申请号：US17328428

申请日：2021-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Lin Lee ,  Chih Chieh Yeh ,  Feng Yuan ,  Hung-Li Chiang ,  Wei-Jen Lai

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L21/762 ,  H01L21/306 ,  H01L21/02

Abstract: An integrated circuit device includes a substrate having a first portion in a first device region and a second portion in a second device region. A first semiconductor strip is in the first device region. A dielectric liner has an edge contacting a sidewall of the first semiconductor strip, wherein the dielectric liner is configured to apply a compressive stress or a tensile stress to the first semiconductor strip. A Shallow Trench Isolation (STI) region is over the dielectric liner, wherein a sidewall and a bottom surface of the STI region is in contact with a sidewall and a top surface of the dielectric liner.

公开(公告)号：US20230101134A1

公开(公告)日：2023-03-30

申请号：US17986451

申请日：2022-11-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hsin Yang ,  Yen-Ming Chen ,  Feng-Cheng Yang ,  Tsung-Lin Lee ,  Wei-Yang Lee ,  Dian-Hau Chen

IPC: H01L29/49 ,  G06F30/392 ,  H01L21/764 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66

Abstract: A semiconductor device includes a substrate. A gate structure is disposed over the substrate in a vertical direction. The gate structure extends in a first horizontal direction. An air spacer is disposed adjacent to a first portion of the gate structure in a second horizontal direction that is different from the first horizontal direction. The air spacer has a vertical boundary in a cross-sectional side view defined by the vertical direction and the first horizontal direction.

公开(公告)号：US11302535B2

公开(公告)日：2022-04-12

申请号：US16158802

申请日：2018-10-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzung-Yi Tsai ,  Yen-Ming Chen ,  Tsung-Lin Lee ,  Po-Kang Ho

IPC: H01L21/32 ,  H01L21/324 ,  H01L29/78 ,  H01L29/66 ,  H01L29/161 ,  H01L29/51 ,  H01L21/768

Abstract: A semiconductor device is provided. The semiconductor device has a fin structure that protrudes vertically upwards. A lateral dimension of the fin structure is reduced. A semiconductor layer is formed on the fin structure after the reducing of the lateral dimension. An annealing process is performed to the semiconductor device after the forming of the semiconductor layer. A dielectric layer is formed over the fin structure after the performing of the annealing process.

公开(公告)号：US10991811B2

公开(公告)日：2021-04-27

申请号：US16528768

申请日：2019-08-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Ching Cheng ,  Wei-Sheng Yun ,  Shao-Ming Yu ,  Tsung-Lin Lee ,  Chih-Chieh Yeh

IPC: H01L29/66 ,  H01L21/762 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786 ,  B82Y10/00 ,  H01L29/08 ,  H01L27/06 ,  H01L27/092 ,  H01L21/822 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/40 ,  H01L29/165

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a plurality of nanowires over an input-output region, and a protective layer surrounding the nanowires. The protective layer is made of silicon, silicon germanium, silicon oxide, silicon nitride, silicon sulfide, or a combination thereof. The semiconductor device structure also includes a high-k dielectric layer surrounding the protective layer, and a gate electrode surrounding the high-k dielectric layer. The semiconductor device structure further includes a source/drain portion adjacent to the gate electrode, and an interlayer dielectric layer over the source/drain portion.

公开(公告)号：US20200290095A1

公开(公告)日：2020-09-17

申请号：US16886743

申请日：2020-05-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Lin Lee ,  Yi-Ming Lin ,  Chih-Hung Yeh ,  Zi-Yuang Wang

IPC: B08B3/08 ,  B08B9/08 ,  H01J37/32 ,  C23C16/44

Abstract: A method of forming a process film includes the following operations. A substrate is transferred into a process chamber having an interior surface. A process film is formed over the substrate, and the process film is also formed on the interior surface of the process chamber. The substrate is transferred out of the process chamber. A non-process film is formed on the interior surface of the process chamber. In some embodiments, porosity of the process film is greater than a porosity of the non-process film.

公开(公告)号：US20190291145A1

公开(公告)日：2019-09-26

申请号：US15925785

申请日：2018-03-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Lin Lee ,  Yi-Ming Lin ,  Chih-Hung Yeh ,  Zi-Yuang Wang

IPC: B08B3/08 ,  B08B9/08

Abstract: A method of cleaning a process chamber includes following steps. A plurality of process films and a plurality of non-process films are alternately formed on an interior surface of the process chamber. A cleaning operation is performed to remove the plurality of process films and the plurality of non-process films from the interior surface of the process chamber.

公开(公告)号：US10395937B2

公开(公告)日：2019-08-27

申请号：US15689334

申请日：2017-08-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzung-Yi Tsai ,  Yen-Ming Chen ,  Dian-Hau Chen ,  Han-Ting Tsai ,  Tsung-Lin Lee ,  Chia-Cheng Ho ,  Ming-Shiang Lin

IPC: H01L21/308 ,  H01L21/311 ,  H01L27/092 ,  H01L21/3115

Abstract: A method of forming a semiconductor device is disclosed. The method includes providing a device having a substrate and a hard mask layer over the substrate; forming a mandrel over the hard mask layer; depositing a material layer on sidewalls of the mandrel; implanting a dopant into the material layer; performing an etching process on the hard mask layer using the mandrel and the material layer as an etching mask, thereby forming a patterned hard mask layer, wherein the etching process concurrently produces a dielectric layer deposited on sidewalls of the patterned hard mask layer, the dielectric layer containing the dopant; and forming a fin by etching the substrate using the patterned hard mask layer and the dielectric layer collectively as an etching mask.

公开(公告)号：US09847334B1

公开(公告)日：2017-12-19

申请号：US15356252

申请日：2016-11-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shahaji B. More ,  Zheng-Yang Pan ,  Tsung-Lin Lee ,  Shih-Chieh Chang

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/165 ,  H01L21/324

CPC classification number: H01L27/0924 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0928 ,  H01L29/165

Abstract: Structures and formation methods of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate with a first lattice constant and having a PMOS region and an NMOS region. The semiconductor device further includes first and second fin structures over the PMOS region and NMOS region respectively. The first fin structure includes a buffer layer with a second lattice constant and a first channel layer. The lattice constant difference between the first channel layer and the buffer layer is smaller than that between the first channel layer and the semiconductor layer. The first channel layer has a third lattice constant, which is greater than the second lattice constant. The first lattice constant is greater than the second lattice constant. The second fin structure includes a second channel layer. The second channel layer has a fourth lattice constant which is less than the first lattice constant.

公开(公告)号：US20240379802A1

公开(公告)日：2024-11-14

申请号：US18783194

申请日：2024-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Lin Lee ,  Choh Fei Yeap ,  Da-Wen Lin ,  Chih Yeh

IPC: H01L29/423 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/786

Abstract: A first gate-all-around (GAA) transistor is formed on the first fin structure; the first GAA transistor has a channel region within a first plurality of nanostructures. A second GAA transistor is formed on the second fin structure; the second GAA transistor has a second channel region configuration. The second GAA transistor has a channel region within a second plurality of nanostructures. The second plurality of nanostructures is less than the first plurality of nanostructures.

公开(公告)号：US12142490B2

公开(公告)日：2024-11-12

申请号：US17717375

申请日：2022-04-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzung-Yi Tsai ,  Yen-Ming Chen ,  Tsung-Lin Lee ,  Po-Kang Ho

IPC: H01L21/32 ,  H01L21/324 ,  H01L21/768 ,  H01L29/161 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device is provided. The semiconductor device has a fin structure that protrudes vertically upwards. A lateral dimension of the fin structure is reduced. A semiconductor layer is formed on the fin structure after the reducing of the lateral dimension. An annealing process is performed to the semiconductor device after the forming of the semiconductor layer. A dielectric layer is formed over the fin structure after the performing of the annealing process.