公开(公告)号：US20150147882A1

公开(公告)日：2015-05-28

申请号：US14087334

申请日：2013-11-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsin-Chieh Yao ,  Chung-Ju Lee ,  Yung-Hsu Wu ,  Tien-I Bao ,  Shau-Lin Shue

IPC分类号： H01L21/768

CPC分类号： H01L21/0274 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76879 ,  H01L2224/29575 ,  H01L2224/37572 ,  H01L2225/1058

摘要： A method includes performing a double patterning process to form a first mandrel, a second mandrel, and a third mandrel, with the second mandrel being between the first mandrel and the second mandrel, and etching the second mandrel to cut the second mandrel into a fourth mandrel and a fifth mandrel, with an opening separating the fourth mandrel from the fifth mandrel. A spacer layer is formed on sidewalls of the first, the mandrel, the fourth, and the fifth mandrels, wherein the opening is fully filled by the spacer layer. Horizontal portions of the spacer layer are removed, with vertical portions of the spacer layer remaining un-removed. A target layer is etched using the first, the second, the fourth, and the fifth mandrels and the vertical portions of the spacer layer as an etching mask, with trenches formed in the target layer. The trenches are filled with a filling material.

摘要翻译： 一种方法包括执行双重图案化处理以形成第一心轴，第二心轴和第三心轴，其中第二心轴位于第一心轴和第二心轴之间，并且蚀刻第二心轴以将第二心轴切割成第四心轴 心轴和第五心轴，具有将第四心轴与第五心轴分开的开口。 间隔层形成在第一，心轴，第四和第五心轴的侧壁上，其中开口被间隔层完全填充。 间隔层的水平部分被去除，间隔层的垂直部分保持未被去除。 使用第一，第二，第四和第五心轴以及间隔层的垂直部分作为蚀刻掩模蚀刻靶层，其中在目标层中形成沟槽。 沟槽填充有填充材料。

公开(公告)号：US20220344170A1

公开(公告)日：2022-10-27

申请号：US17861586

申请日：2022-07-11

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yung-Sung Yen ,  Chung-Ju Lee ,  Chun-Kuang Chen ,  Chia-Tien Wu ,  Ta-Ching Yu ,  Kuei-Shun Chen ,  Ru-Gun Liu ,  Shau-Lin Shue ,  Tsai-Sheng Gau ,  Yung-Hsu Wu

IPC分类号： H01L21/311 ,  H01L21/033 ,  H01L21/3213 ,  H01L21/768

摘要： A method includes forming a material layer over a substrate, forming a first hard mask (HM) layer over the material layer, forming a first trench, along a first direction, in the first HM layer. The method also includes forming first spacers along sidewalls of the first trench, forming a second trench in the first HM layer parallel to the first trench, by using the first spacers to guard the first trench. The method also includes etching the material layer through the first trench and the second trench, removing the first HM layer and the first spacers, forming a second HM layer over the material layer, forming a third trench in the second HM layer. The third trench extends along a second direction that is perpendicular to the first direction and overlaps with the first trench. The method also includes etching the material layer through the third trench.

公开(公告)号：US10170306B2

公开(公告)日：2019-01-01

申请号：US15489037

申请日：2017-04-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chung-Ju Lee ,  Hsin-Chieh Yao ,  Shau-Lin Shue ,  Tien-I Bao ,  Yung-Hsu Wu

IPC分类号： H01L21/027 ,  H01L21/033 ,  H01L21/768 ,  H01L21/311

摘要： A method includes performing a double patterning process to form a first mandrel, a second mandrel, and a third mandrel, with the third mandrel being between the first mandrel and the second mandrel, and etching the third mandrel to cut the third mandrel into a fourth mandrel and a fifth mandrel, with an opening separating the fourth mandrel from the fifth mandrel. A spacer layer is formed on sidewalls of the first, the second, the fourth, and the fifth mandrels, wherein the opening is fully filled by the spacer layer. Horizontal portions of the spacer layer are removed, with vertical portions of the spacer layer remaining un-removed. A target layer is etched using the first, the second, the fourth, and the fifth mandrels and the vertical portions of the spacer layer as an etching mask, with trenches formed in the target layer. The trenches are filled with a filling material.

公开(公告)号：US20180012761A1

公开(公告)日：2018-01-11

申请号：US15714821

申请日：2017-09-25

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Sheng Chang ,  Cheng-Hsiung Tsai ,  Chung-Ju Lee ,  Hai-Ching Chen ,  Hsiang-Huan Lee ,  Ming-Feng Shieh ,  Ru-Gun Liu ,  Shau-Lin Shue ,  Tien-I Bao ,  Tsai-Sheng Gau ,  Yung-Hsu Wu

IPC分类号： H01L21/033 ,  H01L21/306 ,  H01L21/02 ,  H01L21/3213

CPC分类号： H01L21/0338 ,  H01L21/02186 ,  H01L21/02282 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/30604 ,  H01L21/32139

摘要： A method embodiment for patterning a semiconductor device includes patterning a dummy layer over a hard mask to form one or more dummy lines. A sidewall aligned spacer is conformably formed over the one or more dummy lines and the hard mask. A first reverse material layer is formed over the sidewall aligned spacer. A first photoresist is formed and patterned over the first reverse material layer. The first reverse material layer using the first photoresist as a mask, wherein the sidewall aligned spacer is not etched. The one or more dummy lines are removed, and the hard mask is patterned using the sidewall aligned spacer and the first reverse material layer as a mask. A material used for forming the sidewall aligned spacer has a higher selectivity than a material used for forming the first reverse material layer.

公开(公告)号：US09773676B2

公开(公告)日：2017-09-26

申请号：US14877416

申请日：2015-10-07

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yu-Sheng Chang ,  Cheng-Hsiung Tsai ,  Chung-Ju Lee ,  Hai-Ching Chen ,  Hsiang-Huan Lee ,  Ming-Feng Shieh ,  Ru-Gun Liu ,  Shau-Lin Shue ,  Tien-I Bao ,  Tsai-Sheng Gau ,  Yung-Hsu Wu

IPC分类号： H01L21/311 ,  H01L21/033 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3213

CPC分类号： H01L21/0338 ,  H01L21/02186 ,  H01L21/02282 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/30604 ,  H01L21/32139

摘要： A method embodiment for patterning a semiconductor device includes patterning a dummy layer over a hard mask to form one or more dummy lines. A sidewall aligned spacer is conformably formed over the one or more dummy lines and the hard mask. A first reverse material layer is formed over the sidewall aligned spacer. A first photoresist is formed and patterned over the first reverse material layer. The first reverse material layer using the first photoresist as a mask, wherein the sidewall aligned spacer is not etched. The one or more dummy lines are removed, and the hard mask is patterned using the sidewall aligned spacer and the first reverse material layer as a mask. A material used for forming the sidewall aligned spacer has a higher selectivity than a material used for forming the first reverse material layer.

公开(公告)号：US20170221702A1

公开(公告)日：2017-08-03

申请号：US15489037

申请日：2017-04-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chung-Ju Lee ,  Hsin-Chieh Yao ,  Shau-Lin Shue ,  Tien-I Bao ,  Yung-Hsu Wu

IPC分类号： H01L21/027 ,  H01L21/033 ,  H01L21/768 ,  H01L21/311

CPC分类号： H01L21/0274 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76879 ,  H01L2224/29575 ,  H01L2224/37572 ,  H01L2225/1058

摘要： A method includes performing a double patterning process to form a first mandrel, a second mandrel, and a third mandrel, with the third mandrel being between the first mandrel and the second mandrel, and etching the third mandrel to cut the third mandrel into a fourth mandrel and a fifth mandrel, with an opening separating the fourth mandrel from the fifth mandrel. A spacer layer is formed on sidewalls of the first, the second, the fourth, and the fifth mandrels, wherein the opening is fully filled by the spacer layer. Horizontal portions of the spacer layer are removed, with vertical portions of the spacer layer remaining un-removed. A target layer is etched using the first, the second, the fourth, and the fifth mandrels and the vertical portions of the spacer layer as an etching mask, with trenches formed in the target layer. The trenches are filled with a filling material.

公开(公告)号：US20170186622A1

公开(公告)日：2017-06-29

申请号：US15457084

申请日：2017-03-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tsung-Min Huang ,  Chung-Ju Lee ,  Yung-Hsu Wu

IPC分类号： H01L21/311 ,  H01L21/027 ,  H01L21/768 ,  H01L21/02

CPC分类号： H01L21/31144 ,  H01L21/02118 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31116 ,  H01L21/76816 ,  H01L21/76877

摘要： A method of patterning a semiconductor device is disclosed. A tri-layer photoresist is formed over a plurality of patterned features. The tri-layer photoresist includes a bottom layer, a middle layer disposed over the bottom layer, and a top layer disposed over the middle layer, the top layer containing a photo-sensitive material. The top layer is patterned via a photolithography process, the patterned top layer including an opening. The opening is extended into the bottom layer by etching the bottom layer and continuously forming a protective layer on etched surfaces of the bottom layer and on exposed surfaces of the patterned features. The bottom layer is removed. At least some portions of the protective layer remain on the exposed surfaces of the patterned features after the bottom layer is removed.

公开(公告)号：US20170025346A1

公开(公告)日：2017-01-26

申请号：US14803671

申请日：2015-07-20

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsin-Chieh Yao ,  Carlos H. Diaz ,  Cheng-Hsiung Tsai ,  Chung-Ju Lee ,  Chien-Hua Huang ,  Hsi-Wen Tien ,  Shau-Lin Shue ,  Tien-I Bao ,  Yung-Hsu Wu

IPC分类号： H01L23/528 ,  H01L21/3213 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC分类号： H01L23/528 ,  H01L21/32133 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/7682 ,  H01L21/76883 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/53233 ,  H01L23/53295

摘要： A method of fabricating a semiconductor device is disclosed. The method includes forming a first dielectric layer over a substrate, forming a first trench in the first dielectric layer, forming a metal line in the first trench, removing a first portion of the metal line to form a second trench and removing a second portion of the metal line to form a third trench. A third portion of the metal line is disposed between the second and third trenches. The method also includes forming a second dielectric layer in the second and third trenches.

摘要翻译： 公开了制造半导体器件的方法。 该方法包括在衬底上形成第一电介质层，在第一介电层中形成第一沟槽，在第一沟槽中形成金属线，去除金属线的第一部分以形成第二沟槽， 金属线形成第三沟槽。 金属线的第三部分设置在第二和第三沟槽之间。 该方法还包括在第二和第三沟槽中形成第二电介质层。

公开(公告)号：US20160358788A1

公开(公告)日：2016-12-08

申请号：US15237898

申请日：2016-08-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yung-Sung Yen ,  Chung-Ju Lee ,  Chun-Kuang Chen ,  Chia-Tien Wu ,  Ta-Ching Yu ,  Kuei-Shun Chen ,  Ru-Gun Liu ,  Shau-Lin Shue ,  Tsai-Sheng Gau ,  Yung-Hsu Wu

IPC分类号： H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/033

CPC分类号： H01L21/31144 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L21/76816 ,  H01L21/823481 ,  H01L21/823878

摘要： A method includes forming a material layer over a substrate, forming a first hard mask (HM) layer over the material layer, forming a first trench, along a first direction, in the first HM layer. The method also includes forming first spacers along sidewalls of the first trench, forming a second trench in the first HM layer parallel to the first trench, by using the first spacers to guard the first trench. The method also includes etching the material layer through the first trench and the second trench, removing the first HM layer and the first spacers, forming a second HM layer over the material layer, forming a third trench in the second HM layer. The third trench extends along a second direction that is perpendicular to the first direction and overlaps with the first trench. The method also includes etching the material layer through the third trench.

摘要翻译： 一种方法包括在衬底上形成材料层，在材料层上形成第一硬掩模（HM）层，沿第一方向在第一HM层中形成第一沟槽。 该方法还包括沿着第一沟槽的侧壁形成第一间隔物，通过使用第一间隔件来保护第一沟槽，形成平行于第一沟槽的第一HM层中的第二沟槽。 该方法还包括通过第一沟槽和第二沟槽蚀刻材料层，去除第一HM层和第一间隔物，在材料层上形成第二HM层，在第二HM层中形成第三沟槽。 第三沟槽沿着垂直于第一方向的第二方向延伸并且与第一沟槽重叠。 该方法还包括通过第三沟槽蚀刻材料层。

公开(公告)号：US09431297B2

公开(公告)日：2016-08-30

申请号：US14504067

申请日：2014-10-01

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yung-Hsu Wu ,  Cheng-Hsiung Tsai ,  Yu-Sheng Chang ,  Chia-Tien Wu ,  Chung-Ju Lee ,  Yung-Sung Yen ,  Chun-Kuang Chen ,  Tien-I Bao ,  Ru-Gun Liu ,  Shau-Lin Shue

IPC分类号： H01L21/4763 ,  H01L21/768 ,  H01L21/02 ,  H01L21/311

CPC分类号： H01L21/76877 ,  H01L21/02115 ,  H01L21/02186 ,  H01L21/0228 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76816 ,  H01L23/5283 ,  H01L2221/1063

摘要： Methods of semiconductor device fabrication are provided including those that provide a substrate having a plurality of trenches disposed in a dielectric layer formed above the substrate. A via pattern including a plurality of openings may be defined above the substrate. A spacer material layer is formed on a sidewall at least one trench. Via holes can be etched in the dielectric layer using the via pattern and spacer material layer as a masking element.

摘要翻译： 提供了半导体器件制造方法，其包括提供具有设置在形成在衬底上方的电介质层中的多个沟槽的衬底的方法。 可以在衬底上限定包括多个开口的通孔图案。 在侧壁上形成间隔材料层至少一个沟槽。 可以使用通孔图案和间隔材料层作为掩模元件在电介质层中蚀刻通孔。