公开(公告)号：US20090045423A1

公开(公告)日：2009-02-19

申请号：US12159919

申请日：2006-12-27

Applicant: Takashi Hashimoto ,  Takaki Yasuda

Inventor： Takashi Hashimoto ,  Takaki Yasuda

IPC: H01L33/00

CPC classification number: H01L33/60 ,  H01L2224/13 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An object of the present invention is to provide a light-emitting device with a high output and a high efficiency by improving the efficiency for utilizing light emitted from a semiconductor light-emitting element.The inventive semiconductor light-emitting device comprises a package substrate, a sub-mount provided on the package substrate, a semiconductor light-emitting element provided on the sub-mount, and a reflector surrounding the sub-mount and the semiconductor light-emitting element, wherein the positions and sizes of the sub-mount, light-emitting element and reflector satisfy the following relationship (A) on a cross section perpendicular to the package substrate that passes through the center of the semiconductor light-emitting element, r−1s≦(hs−d)×(1s−1c)/hc  (A) wherein r, 1s and 1c are distances from the drooping portion of the reflector, from the outer circumference of the sub-mount and from the outer circumference of the semiconductor light-emitting element to the center of the semiconductor light-emitting element, respectively, hs and d are heights of the sub-mount and of the drooping portion of the reflector, respectively, and hc is a height of the upper surface of the semiconductor light-emitting element from the upper surface of the sub-mount.

Abstract translation: 本发明的目的是通过提高利用从半导体发光元件发出的光的效率来提供具有高输出和高效率的发光装置。 本发明的半导体发光装置包括封装基板，设置在封装基板上的副安装座，设置在副安装座上的半导体发光元件以及围绕副安装座和半导体发光元件的反射器 其中，子载体，发光元件和反射体的位置和尺寸在垂直于穿过半导体发光元件的中心的封装衬底的横截面上满足以下关系式（A）：< -line-formula description =“In-line Formulas”end =“lead”？> r-1s <=（hs-d）x（1s-1c）/ hc（A）<？in-line-formula description = 其中r，1s和1c是与反射器的下垂部分相距离子载体的外圆周和半导体发光元件的外圆周的距离， 半导体发光元件的中心分别为hs和d为子的高度 和反射器的下垂部分的高度，hc是半导体发光元件的上表面的高度。

公开(公告)号：US20080289285A1

公开(公告)日：2008-11-27

申请号：US12110761

申请日：2008-04-28

Applicant: Masao TERAZAWA ,  Takashi Hashimoto ,  Akihiko Asakura ,  Satoshi Osanai

Inventor： Masao TERAZAWA ,  Takashi Hashimoto ,  Akihiko Asakura ,  Satoshi Osanai

IPC: B60J10/00

CPC classification number: B60J10/78 ,  B60J10/25 ,  B60J10/30

Abstract: A weather strip includes a bottom wall that faces or is in contact with an end face of a fixed window glass that closes a window opening of a side door. An outer wall extends from the bottom wall on an outer side of the vehicle body with respect to the fixed window glass, and an inner wall extends from the bottom wall on an inner side of the vehicle body with respect to the fixed window glass so that the inner wall and the outer wall sandwich a peripheral portion of the fixed window glass in a thickness direction. The inner wall is provided with a spacing groove for creating a space between the fixed window glass and the inner wall.

Abstract translation: 防风条包括面向或与固定窗玻璃的端面接触的底壁，该固定窗玻璃封闭侧门的窗口。 外壁相对于固定窗玻璃从车身外侧的底壁延伸，内壁相对于固定窗玻璃从车身内侧的底壁延伸，使得 内壁和外壁夹着固定窗玻璃的厚度方向的周边部分。 内壁设置有用于在固定窗玻璃和内壁之间产生空间的间隔凹槽。

公开(公告)号：US20080110865A1

公开(公告)日：2008-05-15

申请号：US11665683

申请日：2006-04-05

Applicant: Takashi Hashimoto ,  Tatsushi Satou ,  Akihiko Iwata ,  Yoshikazu Ukai ,  Yasuo Onodera

Inventor： Takashi Hashimoto ,  Tatsushi Satou ,  Akihiko Iwata ,  Yoshikazu Ukai ,  Yasuo Onodera

IPC: B23H1/00

CPC classification number: B23H7/04 ,  B23H1/022

Abstract: A discharge-generation control unit applies at least a preliminary-discharge voltage pulse and a main-discharge voltage pulse between a wire electrode and a work. A discharge-position determining unit determines a discharge position from results of measurement by a plurality of current measuring units. A machining-energy adjusting unit adjusts machining energy generated by the main-discharge voltage pulse based on a discharge position determined before applying the main-discharge voltage pulse, and reflects a result of the adjustment on the generation of an electric discharge by feeding the result to the discharge-generation control unit.

Abstract translation: 放电产生控制单元在线电极和工件之间至少施加预放电电压脉冲和主放电电压脉冲。 放电位置确定单元通过多个电流测量单元从测量结果确定放电位置。 加工能量调节单元基于在施加主放电电压脉冲之前确定的放电位置来调整由主放电电压脉冲产生的加工能量，并且通过馈送结果来反映对放电产生的调整结果 到放电产生控制单元。

公开(公告)号：US07369817B2

公开(公告)日：2008-05-06

申请号：US11012120

申请日：2004-12-16

Applicant: Kumiko Takikawa ,  Satoshi Tanaka ,  Takashi Hashimoto ,  Yoshiyuki Okabe

Inventor： Kumiko Takikawa ,  Satoshi Tanaka ,  Takashi Hashimoto ,  Yoshiyuki Okabe

IPC: H04B1/38

CPC classification number: H01L24/49 ,  H01L23/50 ,  H01L23/66 ,  H01L24/48 ,  H01L2223/6611 ,  H01L2223/6644 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49176 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A pin layout which prevents degradation of a frequency characteristic of a low noise amplifier and a receiving mixer included in a semiconductor integrated circuit for dual-band transmission/reception wherein the circuit of the low noise amplifier is provided at a position where the distance from the end of a pin outside the package of the low noise amplifier to the pad is the shortest; ground pins of two low noise amplifiers and the high frequency signal pins are arranged respectively so as not to be adjacent to each other; the power source and ground pin of the low noise amplifier, and the power source and ground pin of the bias circuit are respectively separated; and high frequency signal wires do not intersect each other.

Abstract translation: 一种防止低噪声放大器和接收混频器的频率特性劣化的引脚布局，包括在用于双频带发送/接收的半导体集成电路中，其中低噪声放大器的电路设置在距离 低端放大器封装外的引脚到焊盘最短; 两个低噪声放大器的接地引脚和高频信号引脚分别布置为不彼此相邻; 低噪声放大器的电源和接地引脚以及偏置电路的电源和接地引脚分别分开; 高频信号线不会相交。

公开(公告)号：US07356921B2

公开(公告)日：2008-04-15

申请号：US10414461

申请日：2003-04-15

Applicant: Masahiro Furusawa ,  Takashi Hashimoto

Inventor： Masahiro Furusawa ,  Takashi Hashimoto

IPC: H05K3/02 ,  H05K3/10

CPC classification number: H05K3/125 ,  H01L21/288 ,  H01L21/4846 ,  H01L21/76838 ,  H05K1/0306 ,  H05K3/105 ,  H05K3/1208 ,  H05K3/38 ,  H05K3/4053 ,  H05K2201/0116 ,  H05K2203/013 ,  H05K2203/121 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49155

Abstract: A method for forming a conductive layer pattern by selectively depositing droplets containing conductive material onto a porous receiving layer. Much of the conductive material is left on the surface for forming wiring patterns but some of it permeates the pockets or voids in the receiving layer and can be used, for example, to provide interlayer connections in laminated wiring boards. Preferably, the conductive material is provided by fine conductive particles, organometallic compounds or mixtures thereof.

Abstract translation: 一种用于通过选择性地将包含导电材料的液滴沉积到多孔接收层上来形成导电层图案的方法。 大部分导电材料留在用于形成布线图案的表面上，但是其中的一些渗透到接收层中的凹穴或空隙中，并且可以用于例如在叠层布线板中提供层间连接。 优选地，导电材料由细小的导电颗粒，有机金属化合物或其混合物提供。

公开(公告)号：US20070269972A1

公开(公告)日：2007-11-22

申请号：US11797588

申请日：2007-05-04

Applicant: Yoshiyuki Kawashima ,  Yasushi Ishii ,  Koichi Toba ,  Satoru Machida ,  Takashi Hashimoto

Inventor： Yoshiyuki Kawashima ,  Yasushi Ishii ,  Koichi Toba ,  Satoru Machida ,  Takashi Hashimoto

IPC: H01L21/44

CPC classification number: H01L27/11568 ,  H01L27/105 ,  H01L27/11573 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/792

Abstract: Provided is a method of manufacturing a semiconductor device having an ONO film composed of a bottom silicon oxide film, a silicon nitride film and a top silicon oxide film over a substrate. The top silicon oxide film of the ONO film is formed in the following manner. A silicon oxide film is formed over the silicon nitride film, and then a hydrogen gas and an oxygen gas are reacted over the silicon nitride film by heating the silicon nitride film (substrate) while reducing the pressure from the atmospheric pressure to grow the silicon oxide film into the top silicon oxide film. According to the present invention, a silicon oxide film having good uniformity and fewer defects can be formed over a silicon-containing underlayer.

Abstract translation: 提供一种制造半导体器件的方法，该半导体器件具有在基底上的由底部氧化硅膜，氮化硅膜和顶部氧化硅膜构成的ONO膜。 ONO膜的顶部氧化硅膜以如下方式形成。 在氮化硅膜上形成氧化硅膜，然后通过加热氮化硅膜（衬底）同时使氢气和氧气在氮化硅膜上反应，同时降低大气压力，使氧化硅生长 胶片进入顶部氧化硅膜。 根据本发明，可以在含硅底层上形成均匀性好，缺陷少的氧化硅膜。

公开(公告)号：US20070228498A1

公开(公告)日：2007-10-04

申请号：US11715348

申请日：2007-03-08

Applicant: Koichi Toba ,  Yasushi Ishii ,  Yoshiyuki Kawashima ,  Satoru Machida ,  Munekatsu Nakagawa ,  Takashi Hashimoto

Inventor： Koichi Toba ,  Yasushi Ishii ,  Yoshiyuki Kawashima ,  Satoru Machida ,  Munekatsu Nakagawa ,  Takashi Hashimoto

IPC: H01L29/94 ,  H01L29/76 ,  H01L31/00

CPC classification number: H01L29/7885 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/42328

Abstract: Provided is a semiconductor device having, over a semiconductor substrate, a control gate electrode and a memory gate electrode which are adjacent to each other and constitute a nonvolatile memory. The height of the memory gate electrode is lower than the height of the control gate electrode. A metal silicide film is formed over the upper surface of the control gate electrode, but not formed over the upper surface of the memory gate electrode. The memory gate electrode has, over the upper surface thereof, a sidewall insulating film made of silicon oxide. This sidewall insulating film is formed in the same step as that for the formation of respective sidewall insulating films over the sidewalls of the memory gate electrode and the control gate electrode. The present invention makes it possible to improve the production yield and performance of the semiconductor device having a nonvolatile memory.

Abstract translation: 提供了一种在半导体衬底上具有彼此相邻并构成非易失性存储器的控制栅电极和存储栅电极的半导体器件。 存储栅电极的高度低于控制栅电极的高度。 在控制栅电极的上表面上形成金属硅化物膜，但不形成在存储栅电极的上表面上。 存储栅电极在其上表面上具有由氧化硅制成的侧壁绝缘膜。 该侧壁绝缘膜以与用于在存储栅电极和控制栅电极的侧壁上形成各个侧壁绝缘膜的步骤相同的步骤形成。 本发明使得可以提高具有非易失性存储器的半导体器件的生产率和性能。

公开(公告)号：US07166893B2

公开(公告)日：2007-01-23

申请号：US10252101

申请日：2002-09-23

Applicant: Yasuhiro Taniguchi ,  Shoji Shukuri ,  Kenichi Kuroda ,  Shuji Ikeda ,  Takashi Hashimoto

Inventor： Yasuhiro Taniguchi ,  Shoji Shukuri ,  Kenichi Kuroda ,  Shuji Ikeda ,  Takashi Hashimoto

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L27/0922 ,  H01L21/26513 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/105 ,  H01L27/10814 ,  H01L27/10894 ,  H01L27/11546 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7835 ,  Y10S438/981

Abstract: A MISFET capable of a high speed operation includes a metal silicide layer in a high concentration region aligned with a gate side wall layer on a self-alignment basis. A MISFET which can be driven at a high voltage includes an LDD portion having a width greater than the width of the side wall layer, a high concentration region in contact with the LDD portion and a metal silicide layer in the high concentration region.

Abstract translation: 能够进行高速运转的MISFET包括在自对准的基础上与栅极侧壁层对准的高浓度区域的金属硅化物层。 可以以高电压驱动的MISFET包括具有大于侧壁层的宽度的宽度的LDD部分，与LDD部分接触的高浓度区域和高浓度区域中的金属硅化物层。

公开(公告)号：US20060164545A1

公开(公告)日：2006-07-27

申请号：US10541371

申请日：2003-12-22

Applicant: Masashi Hoshino ,  Takashi Hashimoto

Inventor： Masashi Hoshino ,  Takashi Hashimoto

IPC: H04N11/02

CPC classification number: H04N7/147 ,  H04N5/445 ,  H04N5/44508 ,  H04N5/45 ,  H04N5/765 ,  H04N5/772 ,  H04N5/907 ,  H04N9/8042 ,  H04N9/8227 ,  H04N9/8233 ,  H04N21/42653 ,  H04N21/4334 ,  H04N21/8146

Abstract: An encoding unit (44) individually encodes display image-forming image data, i.e., image data from an image input unit (2), decoded data from a decoding unit (46), and graphics image data from a graphics-generating unit (47). A storing unit (45) stores the individually encoded image data. As a result, when a user intends to reuse, more specifically, replay, edit, or transmit the stored display image, the user can selectively decode required image elements, thereby reusing the selectively decoded image elements. This feature provides improved user-friendliness.

Abstract translation: 编码单元（44）对来自图像输入单元（2）的图像数据，来自解码单元（46）的解码数据和来自图形生成单元（47）的图形图像数据的显示图像形成图像数据分别进行编码 ）。 存储单元（45）存储单​​独编码的图像数据。 结果，当用户打算重用，更具体地，重放，编辑或发送所存储的显示图像时，用户可以选择性地解码所需的图像元素，从而重新使用选择性地解码的图像元素。 此功能提供更好的用户友好性。

公开(公告)号：US20060138568A1

公开(公告)日：2006-06-29

申请号：US11359291

申请日：2006-02-23

Applicant: Yasuhiro Taniguchi ,  Shoji Shukuri ,  Kenichi Kuroda ,  Shuji Ikeda ,  Takashi Hashimoto

Inventor： Yasuhiro Taniguchi ,  Shoji Shukuri ,  Kenichi Kuroda ,  Shuji Ikeda ,  Takashi Hashimoto

IPC: H01L29/76

CPC classification number: H01L27/0922 ,  H01L21/26513 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/105 ,  H01L27/10814 ,  H01L27/10894 ,  H01L27/11546 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7835 ,  Y10S438/981

Abstract: A MISFET capable of a high speed operation includes a metal silicide layer in a high concentration region aligned with a gate side wall layer on a self-alignment basis. A MISFET which can be driven at a high voltage includes an LDD portion having a width greater than the width of the side wall layer, a high concentration region in contact with the LDD portion and a metal silicide layer in the high concentration region.

Abstract translation: 能够进行高速运转的MISFET包括在自对准的基础上与栅极侧壁层对准的高浓度区域的金属硅化物层。 可以以高电压驱动的MISFET包括具有大于侧壁层的宽度的宽度的LDD部分，与LDD部分接触的高浓度区域和高浓度区域中的金属硅化物层。