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    Semiconductor device integrated multilayer wiring board
    33.
    发明授权
    Semiconductor device integrated multilayer wiring board 失效
    半导体器件集成多层布线板

    公开(公告)号：US07022399B2

    公开(公告)日：2006-04-04

    申请号：US10357097

    申请日：2003-02-03

    申请人： Minoru Ogawa ,  Masahiro Izumi ,  Shigeyasu Itoh ,  Shingetsu Yamada ,  Shuuji Suzuki ,  Hiroo Kurosaki

    发明人： Minoru Ogawa ,  Masahiro Izumi ,  Shigeyasu Itoh ,  Shingetsu Yamada ,  Shuuji Suzuki ,  Hiroo Kurosaki

    IPC分类号： B32B15/00 ,  B32B3/00 ,  B32B7/00

    CPC分类号： H05K3/4632 ,  H01L21/4857 ,  H01L23/145 ,  H01L23/49822 ,  H01L24/24 ,  H01L24/82 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H05K1/185 ,  H05K3/041 ,  H05K3/107 ,  H05K3/1258 ,  H05K3/4617 ,  H05K2201/0129 ,  H05K2201/09036 ,  H05K2203/0108 ,  Y10S428/901 ,  Y10T428/24917 ,  Y10T428/249994 ,  H01L2924/00

    摘要： The present invention provides a semiconductor device integrated multilayer wiring board with a high degree of heat resistance, which is capable of low temperature fusion without the occurrence of resin flow, enables high precision, finely detailed conductive wiring, thereby enabling the production of high density, ultra small three dimensional mounting modules and the like, can also be ideally applied to low volume high mix manufacturing configurations, and has little impact on the environment, and also provides a method of manufacturing such a semiconductor device integrated multilayer wiring board. In the semiconductor device integrated multilayer wiring board, a wiring substrate is formed by embedding conductive wiring within an insulating substrate, formed from a thermoplastic resin composition comprising a polyarylketone resin with a crystalline melting peak temperature of at least 260° C. and an amorphous polyetherimide resin as primary constituents, so that the surface of the wiring protrudes to the surface of the resin, and a plurality of these wiring substrates are laminated together, IC chips are mounted onto some of the wiring substrates, the insulating substrates of the wiring substrates are bonded together by thermal fusion, and the conductive wiring of each of the wiring substrates, and the wiring electrically connecting the wiring substrates together, is formed from a conductive material produced by curing a conductive paste.

    摘要翻译： 本发明提供一种具有高耐热性的半导体器件集成多层布线板，其能够在不发生树脂流动的情况下进行低温熔融，能够实现高精度，细致的导电布线，从而能够生产高密度， 超小三维安装模块等也可以理想地应用于低体积高混合物制造配置，并且对环境影响很小，并且还提供了制造这种半导体器件集成多层布线板的方法。 在半导体装置集成多层布线基板中，通过将导电布线嵌入绝缘基板内而形成布线基板，绝缘基板由包含结晶熔融峰值温度为260℃以上的聚芳基酮树脂的热塑性树脂组合物形成，无定形聚醚酰亚胺 树脂作为主要成分，使得布线的表面突出到树脂的表面，并且多个这些布线基板层叠在一起，将IC芯片安装到一些布线基板上，布线基板的绝缘基板 通过热熔接结合在一起，并且每个布线基板的导电布线以及将布线基板电连接在一起的布线由通过固化导电浆料制成的导电材料形成。

    Photographic processing system
    35.
    发明授权
    Photographic processing system 失效
    摄影处理系统

    公开(公告)号：US6031596A

    公开(公告)日：2000-02-29

    申请号：US809552

    申请日：1997-03-13

    申请人： Hideo Ishii ,  Shigeharu Koboshi ,  Minoru Ogawa ,  Shigeru Takeuchi ,  Masahiro Hamasaki

    发明人： Hideo Ishii ,  Shigeharu Koboshi ,  Minoru Ogawa ,  Shigeru Takeuchi ,  Masahiro Hamasaki

    IPC分类号： G03D15/00 ,  G03B27/44

    CPC分类号： G03D15/005

    摘要： In a photographic processing system for processing a photographic film for each order without splicing it to other photographic film, a destination of each of plural photographic films having a different destination from each other is determined based on photographic film destination determining information recorded on a photographic film to be processed.

    摘要翻译： PCT No.PCT / JP97 / 00155 Sec。 371日期1997年3月13日 102（e）1997年3月13日PCT 1997年1月24日PCT PCT。 第WO97 / 27514号公报 日期1997年1月24日在用于处理每个顺序的照相胶片而不将其与其他照相胶片拼接的照相处理系统中，基于摄影胶片目的地确定信息确定具有彼此不同目的地的多个照相胶片中的每一个的目的地 记录在要加工的摄影胶片上。

    Method for manufacturing edge emission type electroluminescent device arrays
    36.
    发明授权
    Method for manufacturing edge emission type electroluminescent device arrays 失效
    用于制造边缘发射型电致发光器件阵列的方法

    公开(公告)号：US5106652A

    公开(公告)日：1992-04-21

    申请号：US509787

    申请日：1990-04-17

    申请人： Koichiro Sakamoto ,  Minoru Ogawa

    发明人： Koichiro Sakamoto ,  Minoru Ogawa

    IPC分类号： B41J2/44 ,  B41J2/447 ,  B41J2/45 ,  B41J2/455 ,  H05B33/10 ,  H05B33/26

    CPC分类号： B41J2/45 ,  H05B33/10 ,  H05B33/26

    摘要： A method for manufacturing edge emission type EL device arrays is disclosed. The method initially involves depositing a first and a second lower electrode layer of different properties. The second lower electrode layer is patterned into a common electrode arrangement conductive to a plurality of edge emission type EL devices. On top of the first and second lower electrode layers, an EL device layer and an upper electrode layer are deposited. The first lower electrode layer is patterned together with the EL device layer and upper electrode layer into a plurality of edge emission type EL devices. The parts ranging from the top edge of the light-emitting edges for the EL devices to the inside of the substrate are etched. This provides a highly smooth light-emitting edge for each EL device.