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公开(公告)号：US06992022B2
公开(公告)日：2006-01-31
申请号：US10795430
申请日：2004-03-09
IPC分类号： H01L21/31
CPC分类号： H01L28/60 , C23C16/18 , C23C16/409 , H01L21/28556 , H01L21/31604 , H01L27/10814 , H01L28/55
摘要： A process for forming the lower and upper electrodes of a high dielectric constant capacitor in a semiconductor device from an organoruthenium compound by chemical vapor deposition. This chemical vapor deposition technique employs an organoruthenium compound, an oxidizing gas, and a gas (such as argon) which is hardly adsorbed to the ruthenium surface or a gas (such as ethylene) which is readily adsorbed to the ruthenium surface. This process efficiently forms a ruthenium film with good conformality in a semiconductor device.
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公开(公告)号：US06917065B2
公开(公告)日：2005-07-12
申请号：US10681173
申请日：2003-10-09
IPC分类号： H01L21/00 , H01L21/02 , H01L21/8242 , H01L21/8246 , H01L27/108 , H01L27/115 , H01L29/06 , H01L29/76 , H01L31/062
CPC分类号： H01L27/11502 , H01L27/10805 , H01L27/1085 , H01L27/11507 , H01L28/55 , H01L28/65
摘要： A ferroelectric capacitor of the type having a top electrode, a ferroelectric thin film, and a bottom electrode, is characterized in that said ferroelectric thin film is a perovskite-type oxide containing Pb and said upper and bottom electrodes contain an intermetallic compound composed of Pt and Pb. An electronic device is provided with said ferroelectric capacitor. This construction is designed to solve the following problems. In a non-volatile ferroelectric memory (FeRAM), a degraded layer occurs near the interface between the PZT and the electrode due to hydrogen evolved during processing or due to diffusion of Pb from the PZT into the electrode. A stress due to a difference in lattice constant occurs in the interface between the electrode and the ferroelectric thin film. The degraded layer and the interfacial stress deteriorate the initial polarizing characteristics of the ferroelectric capacitor and also greatly deteriorate the polarizing characteristics after switching cycles.
摘要翻译： 具有顶电极，铁电薄膜和底电极的铁电电容器的特征在于，所述铁电薄膜是含有Pb的钙钛矿型氧化物，所述上下电极含有由Pt构成的金属间化合物 和铅。 电子设备设有所述铁电电容器。 这种结构旨在解决以下问题。 在非易失性铁电存储器（FeRAM）中，由于在处理期间释放的氢或由于PZT向电极扩散Pb而在PZT和电极之间的界面附近出现劣化层。 在电极和铁电薄膜之间的界面产生由于晶格常数的差异引起的应力。 劣化层和界面应力劣化铁电电容器的初始极化特性，并且在开关周期后极大地降低极化特性。
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公开(公告)号：US5849670A
公开(公告)日：1998-12-15
申请号：US572748
申请日：1995-12-14
IPC分类号： C04B35/45 , C01G1/00 , C01G15/00 , H01B12/04 , H01B12/10 , H01F6/06 , H01L39/14 , H01L39/24 , H01B12/00
CPC分类号： H01L39/143 , H01L39/2425 , H01L39/2458 , Y10S428/93 , Y10S505/704 , Y10S505/705 , Y10T428/2929
摘要： In order to provide a crystal oriented high quality thallium group superconducting wire having a high critical current density, thallium group superconducting film is formed on oxide single crystal fiber having plane facets and polygonal cross section in the thallium group superconducting wire, wherein c-axis of the thallium group superconducting film is oriented perpendicularly, and a- and b-axis are oriented in parallel to the longitudinal direction of the above fiber, respectively, and resulting to obtain a high quality thallium group superconducting wire with Jc of 10.sup.5 A/cm.sup.2 or more at 77K.
摘要翻译： 为了提供具有高临界电流密度的晶体取向的高品质铊族超导线，在铊族超导线中具有平面和多边形横截面的氧化物单晶纤维上形成铊基超导膜，其中c轴 铊组超导膜垂直取向，a轴和b轴分别与上述纤维的纵向平行取向，得到JC为105A / cm2的高品质铊基超导线，或 更多在77K。
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34.发明授权Method for reducing thickness of interfacial layer, method for forming high dielectric constant gate insulating film, high dielectric constant gate insulating film, high dielectric constant gate oxide film, and transistor having high dielectric constant gate oxide film 失效降低界面层厚度的方法，形成高介电常数栅极绝缘膜的方法，高介电常数栅极绝缘膜，高介电常数栅极氧化膜和具有高介电常数栅极氧化膜的晶体管公开(公告)号：US08575038B2
公开(公告)日：2013-11-05
申请号：US13482071
申请日：2012-05-29
IPC分类号： H01L21/316
CPC分类号： H01L29/51 , H01L21/02181 , H01L21/02183 , H01L21/02194 , H01L21/022 , H01L21/02266 , H01L21/0228 , H01L21/28194 , H01L21/823842 , H01L21/823857 , H01L29/513 , H01L29/517 , H01L29/7833
摘要： To provide a method for reducing a thickness of an interfacial layer, which contains: (a) forming a film of an oxide of a first metal on a semiconductor layer via an oxide film of a semiconducdor serving as an interfacial layer; and (b) forming a film of an oxide of a second metal on the film of the oxide of the first metal, where the second metal has higher valency than that of the first metal.
摘要翻译： 提供一种减小界面层厚度的方法，该方法包括：（a）在半导体层上形成半导体氧化膜作为界面层的第一金属的氧化膜; 和（b）在所述第一金属的氧化物的膜上形成第二金属的氧化物的膜，其中所述第二金属具有比所述第一金属更高的化合价。
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35.发明申请Method for Reducing Thickness of Interfacial Layer, Method for Forming High Dielectric Constant Gate Insulating Film, High Dielectric Constant Gate Insulating Film, High Dielectric Constant Gate Oxide Film, and Transistor Having High Dielectric Constant Gate Oxide Film 失效降低界面层厚度的方法，形成高介电常数栅极绝缘膜的方法，高介电常数栅极绝缘膜，高介电常数栅极氧化膜和具有高介电常数栅极氧化膜的晶体管公开(公告)号：US20120280372A1
公开(公告)日：2012-11-08
申请号：US13482071
申请日：2012-05-29
IPC分类号： H01L21/316 , H01L29/51
CPC分类号： H01L29/51 , H01L21/02181 , H01L21/02183 , H01L21/02194 , H01L21/022 , H01L21/02266 , H01L21/0228 , H01L21/28194 , H01L21/823842 , H01L21/823857 , H01L29/513 , H01L29/517 , H01L29/7833
摘要： To provide a method for reducing a thickness of an interfacial layer, which contains: (a) forming a film of an oxide of a first metal on a semiconductor layer via an oxide film of a semiconducdor serving as an interfacial layer; and (b) forming a film of an oxide of a second metal on the film of the oxide of the first metal, where the second metal has higher valency than that of the first metal.
摘要翻译： 提供一种减小界面层厚度的方法，该方法包括：（a）在半导体层上形成半导体氧化膜作为界面层的第一金属的氧化膜; 和（b）在所述第一金属的氧化物的膜上形成第二金属的氧化物的膜，其中所述第二金属具有比所述第一金属更高的化合价。
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公开(公告)号：US20070212829A1
公开(公告)日：2007-09-13
申请号：US11715354
申请日：2007-03-08
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L21/823814 , H01L21/823828
摘要： A method of manufacturing an MIS semiconductor device includes forming a high dielectric film on a main surface of a semiconductor substrate, forming a silicon film on the high dielectric film, annealing the semiconductor substrate after the silicon film is formed, processing the high dielectric film and the silicon film into a gate pattern after the semiconductor substrate is annealed, to form a gate insulating film and a gate electrode, and forming source and drain regions on the main surface of the semiconductor substrate using the gate electrode as a mask.
摘要翻译： 一种制造MIS半导体器件的方法包括在半导体衬底的主表面上形成高电介质膜，在高电介质膜上形成硅膜，在形成硅膜之后退火半导体衬底，处理高介电膜和 在半导体衬底退火之后将硅膜形成栅极图案，以形成栅极绝缘膜和栅电极，并且使用栅电极作为掩模在半导体衬底的主表面上形成源区和漏区。
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公开(公告)号：US20050236675A1
公开(公告)日：2005-10-27
申请号：US11114195
申请日：2005-04-26
IPC分类号： H01L27/092 , H01L21/28 , H01L21/316 , H01L21/8238 , H01L29/51 , H01L29/76 , H01L29/78
CPC分类号： H01L29/517 , H01L21/28194 , H01L21/823857 , H01L29/513 , H01L29/7833
摘要： To provide a semiconductor device that enables to suppress a defect density of a gate insulating film of an MISFET, gain a sufficient electric characteristic thereof, and make an Equivalent Oxide Thickness (EOT) of the gate insulating film 1.0 nm or less. The MISFETs are formed to have the gate insulating film formed on a main surface of a silicon substrate, and a gate electrode formed on the gate insulating film, wherein the gate insulating film includes a metal silicate layer formed by a metal oxide layer and a silicon oxide layer and the metal silicate layer is formed so as to have concentration gradients of metal and silicon from a silicon substrate side toward a gate electrode side.
摘要翻译： 为了提供能够抑制MISFET的栅极绝缘膜的缺陷密度的半导体器件，获得足够的电特性，并使栅极绝缘膜的等效氧化物厚度（EOT）为1.0nm以下。 MISFET形成为具有形成在硅衬底的主表面上的栅极绝缘膜和形成在栅极绝缘膜上的栅电极，其中栅极绝缘膜包括由金属氧化物层形成的金属硅酸盐层和硅 氧化物层和金属硅酸盐层形成为具有从硅衬底侧到栅电极侧的金属和硅的浓度梯度。
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公开(公告)号：US06743739B2
公开(公告)日：2004-06-01
申请号：US10101600
申请日：2002-03-21
IPC分类号： H01L2131
CPC分类号： H01L28/60 , C23C16/18 , C23C16/409 , H01L21/28556 , H01L21/31604 , H01L27/10814 , H01L28/55
摘要： A process for forming the lower and upper electrodes of a high dielectric constant capacitor in a semiconductor device from an organoruthenium compound by chemical vapor deposition. This chemical vapor deposition technique employs an organoruthenium compound, an oxidizing gas, and a gas (such as argon) which is hardly adsorbed to the ruthenium surface or a gas (such as ethylene) which is readily adsorbed to the ruthenium surface. This process efficiently forms a ruthenium film with good conformality in a semiconductor device.
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公开(公告)号：US06555429B2
公开(公告)日：2003-04-29
申请号：US09810627
申请日：2001-03-19
申请人： Yuichi Matsui , Masahiko Hiratani , Yasuhiro Shimamoto , Yoshitaka Nakamura , Toshihide Nabatame
发明人： Yuichi Matsui , Masahiko Hiratani , Yasuhiro Shimamoto , Yoshitaka Nakamura , Toshihide Nabatame
IPC分类号： H01L218242
CPC分类号： H01L28/60 , H01L21/28562 , H01L27/10814
摘要： In a semiconductor device including a plurality of memory cells, a deposition preventing film is formed on an interlayer insulating film in which a plurality of holes are formed, or a seed film is selectively formed on the interlayer insulating film and on an inner surface and a bottom surface of the holes. A film of Ru, Ir or Pt is deposited by chemical vapor deposition on the deposition preventing film, or on the interlayer insulating film by utilizing the seed film, under the condition where underlayer dependency occurs. In consequence, lower electrodes are formed in accordance with a pattern of the deposition preventing film or the seed film. A dielectric film is formed on the lower electrodes and the deposition preventing film at a predetermined temperature. The material of the lower electrodes does not lose conduction even when exposed to the predetermined temperature employed for forming the dielectric film. Upper electrodes are further formed on the dielectric film. The upper and lower electrodes and an oxide dielectric film together constitute capacitors of the memory cells.
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40.发明授权Semiconductor device having a capacitor structure including a self-alignment deposition preventing film 有权具有包括自对准防沉积膜的电容器结构的半导体器件公开(公告)号：US06483143B2
公开(公告)日：2002-11-19
申请号：US09810401
申请日：2001-03-19
申请人： Yuichi Matsui , Masahiko Hiratani , Yasuhiro Shimamoto , Yoshitaka Nakamura , Toshihide Nabatame
发明人： Yuichi Matsui , Masahiko Hiratani , Yasuhiro Shimamoto , Yoshitaka Nakamura , Toshihide Nabatame
IPC分类号： H01L27108
CPC分类号： H01L28/60 , H01L21/28562 , H01L27/10814
摘要： In a semiconductor device including a plurality of memory cells, a deposition preventing film is formed on an interlayer insulating film in which a plurality of holes are formed, or a seed film is selectively formed on the interlayer insulating film and on an inner surface and a bottom surface of the holes. A film of Ru, Ir or Pt is deposited by chemical vapor deposition on the deposition preventing film, or on the interlayer insulating film by utilizing the seed film, under the condition where underlayer dependency occurs. In consequence, lower electrodes are formed in accordance with a pattern of the deposition preventing film or the seed film. A dielectric film is formed on the lower electrodes and the deposition preventing film at a predetermined temperature. The material of the lower electrodes does not lose conduction even when exposed to the predetermined temperature employed for forming the dielectric film. Upper electrodes are further formed on the dielectric film. The upper and lower electrodes and an oxide dielectric film together constitute capacitors of the memory cells.
摘要翻译： 在包括多个存储单元的半导体器件中，在形成有多个孔的层间绝缘膜上形成防沉积膜，或者在层间绝缘膜和内表面上选择性地形成晶种膜， 孔的底面。 在发生底层依赖性的条件下，通过化学气相沉积在沉积防止膜上或通过利用种子膜在层间绝缘膜上沉积Ru，Ir或Pt的膜。 因此，根据防沉积膜或种子膜的图案形成下部电极。 在预定温度下在下电极和防沉积膜上形成电介质膜。 即使暴露在用于形成电介质膜的预定温度下，下电极的材料也不会导通。 上电极进一步形成在电介质膜上。 上下电极和氧化物介质膜一起构成存储单元的电容器。
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