公开(公告)号：US07170110B2

公开(公告)日：2007-01-30

申请号：US10983610

申请日：2004-11-09

申请人： Akira Inoue ,  Takeshi Takagi ,  Yoshihiro Hara ,  Minoru Kubo

发明人： Akira Inoue ,  Takeshi Takagi ,  Yoshihiro Hara ,  Minoru Kubo

IPC分类号： H01L29/161 ,  H01L29/772

CPC分类号： H01L29/802 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/092 ,  H01L27/10873 ,  H01L27/11502 ,  H01L27/11507 ,  H01L27/1203 ,  H01L27/1214 ,  H01L27/1222 ,  H01L28/55 ,  H01L29/1054 ,  H01L29/783 ,  H01L29/78687

摘要： A silicon oxide film 102, a Pt film 103x, a Ti film 104x and a PZT film 105x are deposited in this order over a Si substrate 101. The Si substrate 101 is placed in a chamber 106 so that the PZT film 105x is irradiated with an EHF wave 108. The irradiation with the EHF wave locally heats a dielectric film such as the PZT film. As a result, it is possible to improve, for example, the leakage property of the dielectric film without adversely affecting a device formed on the Si substrate 101.

摘要翻译： 依次沉积硅衬底101上的氧化硅膜102，Pt膜103x，Ti膜104x和PZT膜105x。 将Si衬底101放置在室106中，使得PZT膜105x被EHF波108照射。 用EHF波照射局部加热电介质膜，例如PZT膜。 结果，可以改善例如电介质膜的泄漏特性，而不会对形成在Si衬底101上的器件产生不利影响。

公开(公告)号：US07133626B2

公开(公告)日：2006-11-07

申请号：US10902790

申请日：2004-08-02

申请人： Miho Kaiga ,  Takeshi Takagi

发明人： Miho Kaiga ,  Takeshi Takagi

IPC分类号： G03G15/00 ,  H02J1/00

CPC分类号： G03G7/00 ,  G03G7/0053 ,  G03G21/1628 ,  G03G2215/00548 ,  G03G2221/1687

摘要： An image forming apparatus includes an image forming portion for forming an image, an image reading portion for reading an image, displaceable with respect to the image forming portion, and an open/closable member that can be opened or closed with respect to a main body of the image forming portion and displaced toward the image reading portion, wherein the displacement of the open/closable member is effected in relation to the displacement of the image reading portion. In this manner the open/closable member can be opened or closed by a simple operation, without increasing the dimension of the image forming apparatus.

摘要翻译： 图像形成装置包括用于形成图像的图像形成部分，用于读取图像的图像读取部分，可相对于图像形成部分移位;以及打开/关闭部件，其可相对于主体打开或关闭 并且朝向图像读取部分移位，其中打开/关闭部件的位移相对于图像读取部分的位移进行。 以这种方式，可以通过简单的操作来打开或关闭打开/关闭构件，而不增加图像形成装置的尺寸。

公开(公告)号：US20050133834A1

公开(公告)日：2005-06-23

申请号：US10948747

申请日：2004-09-24

申请人： Haruyuki Sorada ,  Takeshi Takagi ,  Akira Inoue ,  Yoshio Kawashima

发明人： Haruyuki Sorada ,  Takeshi Takagi ,  Akira Inoue ,  Yoshio Kawashima

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/51 ,  H01L29/76 ,  H01L29/78 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/66636 ,  H01L21/28202 ,  H01L29/1054 ,  H01L29/518 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7842

摘要： A semiconductor device of this invention includes: a semiconductor substrate; a gate electrode formed on the semiconductor substrate; a pair of source and drain electrodes respectively formed in regions of the semiconductor substrate situated on opposite sides of the gate electrode in a plan view; and a germanium-containing channel layer situated below the gate electrode to sandwich an gate insulator therebetween and intervening between the pair of source and drain electrodes, wherein a silicide layer forming at least a part of the source and drain electrodes has a lower germanium concentration than the channel layer.

摘要翻译： 本发明的半导体器件包括：半导体衬底; 形成在所述半导体衬底上的栅电极; 在平面图中分别形成在位于栅电极的相对侧的半导体衬底的区域中的一对源极和漏极; 以及位于栅极电极下方的含锗沟道层，以夹持栅极绝缘体，并且介于所述一对源极和漏极之间，其中形成所述源极和漏极的至少一部分的硅化物层的锗浓度低于 通道层。

公开(公告)号：US06876045B2

公开(公告)日：2005-04-05

申请号：US10626642

申请日：2003-07-25

申请人： Takeshi Takagi

发明人： Takeshi Takagi

IPC分类号： H01L21/28 ,  H01L21/321 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/49 ,  H01L29/78 ,  H01L29/80 ,  H01L29/72

CPC分类号： H01L29/4983 ,  H01L21/2807 ,  H01L21/28105 ,  H01L21/28114 ,  H01L21/28247 ,  H01L21/32105 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/823864 ,  H01L29/1054 ,  H01L29/7836 ,  H01L29/802

摘要： This specification relates to a process for manufacturing a semiconductor device, comprising the steps of: forming a lower gate electrode film on a semiconductor substrate 10 via a gate insulating film 11; forming an upper gate electrode film on the lower gate electrode film, the upper gate electrode film being made of a material having a lower oxidation rate than that of the lower gate electrode film; forming a gate electrode 12 by patterning the upper gate electrode film and the lower gate electrode film, the gate electrode 12 comprising a lower gate electrode element 12a and an upper gate electrode element 12b; forming source/drain regions 15 by introducing an impurity into the semiconductor substrate 10; and forming oxide film sidewalls 13 by oxidizing the side faces of the lower gate electrode element 12a and the upper gate electrode element 12b, the thickness of the oxide film sidewalls 13 in the gate length direction being larger at the sides of the lower gate electrode element 12a than at the sides of the upper gate electrode element 12b.

摘要翻译： 本说明书涉及半导体器件的制造方法，其特征在于，包括以下步骤：通过栅极绝缘膜11在半导体衬底10上形成下部栅极电极膜; 在下栅电极膜上形成上栅极电极膜，上栅极电极膜由比下栅极电极膜氧化率低的材料制成; 通过图案化上栅极电极膜和下栅极电极膜形成栅电极12，栅电极12包括下栅电极元件12a和上栅极电极元件12b; 通过将杂质引入到半导体衬底10中来形成源/漏区15; 以及通过氧化下部栅极电极元件12a和上部栅极电极元件12b的侧面而形成氧化膜侧壁13，栅极长度方向上的氧化膜侧壁13的厚度在下部栅极电极元件的侧面较大 12a比在上栅极电极元件12b的侧面处。

公开(公告)号：US20050040436A1

公开(公告)日：2005-02-24

申请号：US10866093

申请日：2004-06-14

申请人： Haruyuki Sorada ,  Akira Asai ,  Takeshi Takagi ,  Akira Inoue ,  Yoshio Kawashima

发明人： Haruyuki Sorada ,  Akira Asai ,  Takeshi Takagi ,  Akira Inoue ,  Yoshio Kawashima

IPC分类号： H01L21/8238 ,  H01L27/10

CPC分类号： H01L21/823807

摘要： A semiconductor integrated circuit fabrication method according to this invention includes: a step of forming a pair of first device forming regions and a pair of second device forming regions in a surface layer portion of a semiconductor substrate by surrounding each of the regions by device isolation; a step of forming a first oxide film covering the surface of the semiconductor substrate after the preceding step; a step of removing an intended portion of the first oxide film to expose the pair of second device forming regions; a step of forming a pair of heterojunction structures, by selective epitaxial growth, on the pair of second device forming regions thus exposed; a step of forming a second oxide film covering the surface of the substrate after the preceding step; and a step of forming a pair of gate electrodes above each of the pair of first device forming regions and the pair of second device forming regions, whereby a normal complementary MOS transistor and a heterojunction complementary MOS transistor are eventually formed in the pair of first device forming regions and the pair of second device forming regions, respectively.

摘要翻译： 根据本发明的半导体集成电路制造方法包括：通过器件隔离来围绕每个区域来在半导体衬底的表面层部分中形成一对第一器件形成区域和一对第二器件形成区域的步骤; 在前述步骤之后形成覆盖半导体衬底的表面的第一氧化物膜的步骤; 去除所述第一氧化物膜的预期部分以暴露所述一对第二器件形成区域的步骤; 通过选择性外延生长形成一对异质结结构在由此露出的一对第二器件形成区上的步骤; 在上述步骤之后形成覆盖基板表面的第二氧化膜的步骤; 以及在所述一对第一器件形成区域和所述一对第二器件形成区域中的每一个上形成一对栅电极的步骤，由此在所述一对第一器件形成区域中最终形成正常互补MOS晶体管和异质结互补MOS晶体管 形成区域和一对第二装置形成区域。

公开(公告)号：US20050006709A1

公开(公告)日：2005-01-13

申请号：US10910573

申请日：2004-08-04

申请人： Akira Asai ,  Takeshi Takagi

发明人： Akira Asai ,  Takeshi Takagi

IPC分类号： H01L21/331 ,  H01L21/8222 ,  H01L27/082 ,  H01L29/737 ,  H01L21/8238 ,  H01L27/102 ,  H01L29/70 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/11 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/66242 ,  H01L21/8222 ,  H01L27/0823 ,  H01L27/0826 ,  H01L29/7378

摘要： A semiconductor integrated circuit comprising a plurality of bipolar transistors that are produced by forming, in a plurality of transistor-producing regions (A1 and A2), a first conductive type emitter layer (6) on the front surface side of a second conductive type base layer (4) that is formed on the surface side of a first conductive collector layer (2) and contains germanium, the first conductive type emitter layer (6) being formed from a semiconductor material having a band gap larger than the base layer (4); wherein the concentrations of impurities contained in the emitter layers (6, 61) vary among the plurality of transistor-producing regions (A1, A2), and the germanium concentrations differ in the base-emitter junction interfaces of at least two of the transistor-producing regions (A1, A2), such that the ON-state voltages required for turning the plurality of bipolar transistors into an ON state differ from each other. This semiconductor integrated circuit makes it possible to reduce power consumption while maintaining the excellent performance of a bipolar transistor.

摘要翻译： 一种半导体集成电路，包括多个双极晶体管，其通过在多个晶体管产生区域（A1和A2）中形成在第二导电类型基底的前表面侧上的第一导电类型发射极层（6） 层（4），其形成在第一导电集电体层（2）的表面侧并且包含锗，所述第一导电型发射极层（6）由具有比所述基极层（4）的带隙大的半导体材料形成 ）; 其中，所述发射极层（6,61）中所含的杂质浓度在所述多个晶体管产生区域（A1，A2）中变化，并且所述晶体管 - 半导体区域中的至少两个的基极 - 发射极结界面的锗浓度不同， 产生区域（A1，A2），使得将多个双极晶体管转换为导通状态所需的导通状态电压彼此不同。 该半导体集成电路使得可以在保持双极晶体管的优异性能的同时降低功耗。

公开(公告)号：US06753555B2

公开(公告)日：2004-06-22

申请号：US10268905

申请日：2002-10-11

申请人： Takeshi Takagi ,  Akira Inoue

发明人： Takeshi Takagi ,  Akira Inoue

IPC分类号： H01L310328

CPC分类号： H01L29/1054 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7782 ,  H01L29/783 ,  H01L29/78615 ,  H01L29/78648 ,  H01L29/78687

摘要： A HDTMOS includes a Si substrate, a buried oxide film and a semiconductor layer. The semiconductor layer includes an upper Si film, an epitaxially grown Si buffer layer, an epitaxially grown SiGe film, and an epitaxially grown Si film. Furthermore, the HDTMOS includes an n-type high concentration Si body region, an n− Si region, a SiGe channel region containing n-type low concentration impurities, an n-type low concentration Si cap layer, and a contact which is a conductor member for electrically connecting the gate electrode and the Si body region. The present invention extends the operation range while keeping the threshold voltage small by using, for the channel layer, a material having a smaller potential at the band edge where carriers travel than that of a material constituting the body region.

摘要翻译： HDTMOS包括Si衬底，掩埋氧化物膜和半导体层。 半导体层包括上硅膜，外延生长的Si缓冲层，外延生长的SiGe膜和外延生长的Si膜。 此外，HDTMOS包括n型高浓度Si体区域，n

公开(公告)号：US06512252B1

公开(公告)日：2003-01-28

申请号：US09712223

申请日：2000-11-15

申请人： Takeshi Takagi ,  Akira Inoue

发明人： Takeshi Takagi ,  Akira Inoue

IPC分类号： H01L31072

CPC分类号： H01L29/1054 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7782 ,  H01L29/783 ,  H01L29/78615 ,  H01L29/78648 ,  H01L29/78687

摘要： A HDTMOS includes a Si substrate, a buried oxide film and a semiconductor layer. The semiconductor layer includes an upper Si film, an epitaxially grown Si buffer layer, an epitaxially grown SiGe film, and an epitaxially grown Si film. Furthermore, the HDTMOS includes an n-type high concentration Si body region, an n− Si region, a SiGe channel region containing n-type low concentration impurities, an n-type low concentration Si cap layer, and a contact which is a conductor member for electrically connecting the gate electrode and the Si body region. The present invention extends the operation range while keeping the threshold voltage small by using, for the channel layer, a material having a smaller potential at the band edge where carriers travel than that of a material constituting the body region.

公开(公告)号：US06399993B1

公开(公告)日：2002-06-04

申请号：US09786551

申请日：2001-03-07

申请人： Teruhito Ohnishi ,  Akira Asai ,  Takeshi Takagi ,  Tohru Saitoh ,  Yo Ichikawa ,  Yoshihiro Hara ,  Koichiro Yuki ,  Katsuya Nozawa ,  Koji Katayama ,  Yoshihiko Kanzawa

发明人： Teruhito Ohnishi ,  Akira Asai ,  Takeshi Takagi ,  Tohru Saitoh ,  Yo Ichikawa ,  Yoshihiro Hara ,  Koichiro Yuki ,  Katsuya Nozawa ,  Koji Katayama ,  Yoshihiko Kanzawa

IPC分类号： H01L2972

CPC分类号： H01L21/76237 ,  H01L21/8249

摘要： In a bipolar transistor block, a base layer (20a) of SiGe single crystals and an emitter layer (26) of almost 100% of Si single crystals are stacked in this order over a collector diffused layer (9). Over both edges of the base layer (20a), a base undercoat insulating film (5a) and base extended electrodes (22) made of polysilicon are provided. The base layer (20a) has a peripheral portion with a thickness equal to that of the base undercoat insulating film (5a) and a center portion thicker than the peripheral portion. The base undercoat insulating film (5a) and gate insulating films (5b and 5c) for a CMOS block are made of the same oxide film. A stress resulting from a difference in thermal expansion coefficient between the SiGe layer as the base layer and the base undercoat insulating film 5a can be reduced, and a highly reliable BiCMOS device is realized.

摘要翻译： 在双极晶体管块中，SiGe单晶的基极层（20a）和几乎100％的Si单晶的发射极层（26）依次层叠在集电极扩散层（9）上。 在基底层（20a）的两个边缘上设置有由多晶硅制成的基底底涂层绝缘膜（5a）和基底延伸电极（22）。 基底层（20a）具有与基底底涂层绝缘膜（5a）的厚度相等的周边部分和比周边部分厚的中心部分。 用于CMOS块的基底涂层绝缘膜（5a）和栅极绝缘膜（5b和5c）由相同的氧化物膜制成。 由于作为基底层的SiGe层与基底底涂层绝缘膜5a之间的热膨胀系数的差异导致的应力可以降低，并且实现了高可靠性的BiCMOS器件。

公开(公告)号：US5932658A

公开(公告)日：1999-08-03

申请号：US667934

申请日：1996-06-24

申请人： Yasuo Tanaka ,  Takeshi Takagi ,  Shigeyuki Sasaki ,  Makoto Shimizu ,  Yoshitaka Okude

发明人： Yasuo Tanaka ,  Takeshi Takagi ,  Shigeyuki Sasaki ,  Makoto Shimizu ,  Yoshitaka Okude

IPC分类号： B05D7/00 ,  C08L33/02 ,  C08L33/06 ,  C08L35/00 ,  C09D133/06 ,  C08L33/14

CPC分类号： B05D7/532 ,  C09D133/064 ,  C09D133/068 ,  C08L2205/18 ,  C08L33/02 ,  C08L33/068 ,  C08L35/00

摘要： The present invention provides a curable resin composition having good curability and storage stability, which provides a cured film having excellent weather resistance, acid resistance and mar resistance. The curable resin composition comprises:(a) 20 to 80% by weight of a polycarboxylic acid having an acid value of 25 to 300 mg KOH/g based on solid and a number average molecular weight of 500 to 20000; and(b) 20 to 80% by weight of a polyepoxide having an epoxy equivalent of 100 to 800 and a number average molecular weight of 500 to 20000, prepared by copolymerizing: (1) 10 to 60% by weight of a long-chain epoxy monomer; and (2) 40 to 90% by weight of an ethylenically unsaturated monomer having no epoxy group. The present invention also provides a process for forming a cured film using the resin composition.

摘要翻译： 本发明提供了具有良好的固化性和保存稳定性的固化性树脂组合物，其提供了耐候性，耐酸性和耐擦伤性优异的固化膜。 可固化树脂组合物包含：（a）20至80重量％的基于固体的酸值为25至300mg KOH / g并且数均分子量为500至20000的多元羧酸; 和（b）20〜80重量％的环氧当量为100〜800，数均分子量为500〜20000的聚环氧化物，通过以下方法制备：（1）10〜60重量％的长链 环氧单体; 和（2）40〜90重量％的不具有环氧基的烯属不饱和单体。 本发明还提供了使用该树脂组合物形成固化膜的方法。