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公开(公告)号：US20080258306A1
公开(公告)日：2008-10-23
申请号：US12105538
申请日：2008-04-18
IPC分类号： H01L23/538 , H01L21/56
CPC分类号： H01L23/3114 , H01L21/6835 , H01L23/3135 , H01L23/3185 , H01L24/24 , H01L24/48 , H01L24/82 , H01L24/97 , H01L25/105 , H01L25/50 , H01L2224/02371 , H01L2224/04105 , H01L2224/05001 , H01L2224/05008 , H01L2224/05023 , H01L2224/05026 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05184 , H01L2224/05548 , H01L2224/05569 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05684 , H01L2224/12105 , H01L2224/16145 , H01L2224/48091 , H01L2224/82001 , H01L2224/97 , H01L2225/06562 , H01L2225/1058 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/15311 , H01L2224/82 , H01L2924/01028 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： The present invention provides a semiconductor device and a method for fabricating the same. The semiconductor device includes a chip having an active surface and an opposing non-active surface, wherein a plurality of bond pads are formed on the active surface, and first metal layers are formed on the bond pads and to edges of the non-active surface; conductive traces disposed on the non-active surface of the chip; a dielectric layer covering sides of the chip and formed with a plurality of openings therein to expose a portion of the conductive traces; and a plurality of second metal layers formed in the openings of the dielectric layer and on the first metal layers, such that the bond pads are electrically connected to the conductive traces via the first and second metal layers.
摘要翻译： 本发明提供一种半导体器件及其制造方法。 半导体器件包括具有活性表面和相对的非活性表面的芯片，其中在有源表面上形成多个接合焊盘，并且第一金属层形成在接合焊盘和非活性表面的边缘上 ; 布置在芯片的非有源表面上的导电迹线; 介电层，其覆盖所述芯片的侧面并在其中形成有多个开口以暴露所述导电迹线的一部分; 以及多个第二金属层，形成在电介质层的开口中和第一金属层上，使得接合焊盘经由第一和第二金属层电连接到导电迹线。
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公开(公告)号：US20080251937A1
公开(公告)日：2008-10-16
申请号：US12082724
申请日：2008-04-11
CPC分类号： H01L21/76898 , H01L25/0657 , H01L2224/48091 , H01L2225/06513 , H01L2225/06551 , H01L2225/06562 , H01L2924/00014
摘要： A stackable semiconductor device and a manufacturing method thereof are disclosed. The method includes providing a wafer comprised of a plurality of chips, wherein a plurality of solder pads are formed on the active surface of each chip, and a plurality of grooves are formed between the solder pads of any two adjacent ones of the chips; forming a dielectric layer on regions between the solder pads of any two adjacent ones of the chips ; forming a metal layer on the dielectric layer electrically connected to the solder pads and forming a connective layer on the metal layer, wherein the width of the connective layer is smaller than that of the metal layer; cutting along the grooves to break off the electrical connection between adjacent chips; thinning the non-active surface of the wafer to the extent that the metal layer is exposed from the wafer; and separating the chips to form a plurality of stackable semiconductor devices. Accordingly, a multi-chip stack structure can be obtained by stacking and electrically connecting a plurality of semiconductor devices through the electrical connection between the connective layer of a semiconductor device and the metal layer of another semiconductor device, thereby effectively integrating more chips without having to increase the stacking area, and further the problems of poor electrical connection, complicated manufacturing processes and high costs known in the prior art can be avoided.
摘要翻译： 公开了一种可堆叠半导体器件及其制造方法。 该方法包括提供由多个芯片组成的晶片，其中在每个芯片的有源表面上形成多个焊盘，并且在任何两个相邻芯片的焊盘之间形成多个沟槽; 在任何两个相邻芯片的焊盘之间的区域上形成电介质层; 在与所述焊料焊盘电连接的所述电介质层上形成金属层，并在所述金属层上形成连接层，其中所述连接层的宽度小于所述金属层的宽度; 沿着凹槽切割以破坏相邻芯片之间的电连接; 使晶片的非活性表面变薄至金属层从晶片露出的程度; 并分离所述芯片以形成多个可堆叠半导体器件。 因此，通过半导体器件的连接层与另一半导体器件的金属层之间的电连接层叠并电连接多个半导体器件，可以获得多芯片堆叠结构，从而有效地集成更多的芯片，而不必 增加堆积面积，进一步避免了现有技术中已知的电连接不良，制造工艺复杂，成本高的问题。
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33.发明申请Method for fabricating wafer level semiconductor package with build-up layer 有权用于制造具有堆积层的晶片级半导体封装的方法公开(公告)号：US20070034998A1
公开(公告)日：2007-02-15
申请号：US11580560
申请日：2006-10-12
IPC分类号： H01L23/02
CPC分类号： H01L21/6835 , H01L21/568 , H01L24/19 , H01L24/96 , H01L24/97 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/19 , H01L2224/20 , H01L2224/32225 , H01L2224/32245 , H01L2224/73267 , H01L2224/97 , H01L2924/01029 , H01L2924/01033 , H01L2924/12042 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , H01L2924/351 , H01L2924/3511 , H01L2224/82 , H01L2924/00
摘要： A wafer level semiconductor package with a build-up layer is provided, which includes a glass frame having a through hole for receiving a semiconductor chip therein, a low-modulus buffer material filled within the space formed between the semiconductor chip and the glass frame, a build-up layer formed on the glass frame and the semiconductor chip such that the build-up layer is electrically connected to the semiconductor chip, and a plurality of conductive elements mounted on the build-up layer so that the semiconductor chip is electrically connected to external devices. With the use of the glass frame and low-modulus buffer material, the wafer level semiconductor package thus-obtained is free from warpage, chip-crack, and delamination problems and the reliability thereof is enhanced. A method for fabricating the wafer level semiconductor package is also provided.
摘要翻译： 提供具有积层的晶片级半导体封装，其包括具有用于接收其中的半导体芯片的通孔的玻璃框架，填充在形成在半导体芯片和玻璃框架之间的空间内的低模量缓冲材料， 形成在所述玻璃框架和所述半导体芯片上的堆积层，使得所述积层层电连接到所述半导体芯片，以及安装在所述积层层上的多个导电元件，使得所述半导体芯片电连接 到外部设备。 通过使用玻璃框架和低模量缓冲材料，由此获得的晶片级半导体封装没有翘曲，芯片裂纹和分层问题，并且其可靠性得到提高。 还提供了一种用于制造晶片级半导体封装的方法。
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公开(公告)号：US20060292741A1
公开(公告)日：2006-12-28
申请号：US11471516
申请日：2006-06-21
IPC分类号： H01L21/00
CPC分类号： H01L23/3128 , H01L21/561 , H01L23/4334 , H01L24/48 , H01L24/97 , H01L2224/16 , H01L2224/48227 , H01L2224/97 , H01L2924/00011 , H01L2924/00014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19105 , H01L2924/351 , H01L2224/81 , H01L2924/00 , H01L2924/00012 , H01L2224/0401 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A heat-dissipating semiconductor package and a fabrication method thereof are provided. A semiconductor chip is mounted and electrically connected to a substrate. A heat-dissipating structure includes a heat sink and at least one supporting portion, wherein the supporting portion is attached to the substrate at a position outside a predetermined package area for the semiconductor package, and the semiconductor chip is disposed under the heat sink. An encapsulant is formed on the substrate to encapsulate the semiconductor chip and the heat-dissipating structure, wherein a projection area of the encapsulant on the substrate is larger in size than the predetermined package area. A cutting process is performed along edges of the predetermined package area to remove parts of the encapsulant, the supporting portion and the substrate, which are located outside the predetermined package area, so as to form the semiconductor package integrated with the heat-dissipating structure.
摘要翻译： 提供散热半导体封装及其制造方法。 半导体芯片安装并电连接到基板。 散热结构包括散热器和至少一个支撑部分，其中支撑部分在用于半导体封装的预定封装区域外的位置处附接到基板，并且半导体芯片设置在散热器下方。 在基板上形成密封剂以封装半导体芯片和散热结构，其中密封剂在基板上的投影面积大于预定封装面积。 沿着预定包装区域的边缘进行切割处理以去除位于预定包装区域外部的密封剂，支撑部分和基底的部分，以形成与散热结构集成的半导体封装。
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公开(公告)号：US06989296B2
公开(公告)日：2006-01-24
申请号：US10844877
申请日：2004-05-12
IPC分类号： H01L21/44
CPC分类号： H01L23/055 , H01L21/50 , H01L23/10 , H01L24/45 , H01L24/48 , H01L24/97 , H01L27/14618 , H01L27/14683 , H01L2224/16 , H01L2224/45144 , H01L2224/48091 , H01L2224/73265 , H01L2224/92247 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/15173 , H01L2924/15311 , H01L2924/16152 , H01L2924/16195 , H01L2924/181 , H01L2224/85 , H01L2224/83 , H01L2224/05599 , H01L2924/00
摘要： A fabrication method of a semiconductor package with a photosensitive chip is provided. A substrate having a core is prepared. An interposer is mounted on the substrate, with a peripheral portion of the substrate exposed from the interposer. A molding process is performed and the substrate is clamped between an upper mold and a lower mold, with the interposer received in an upwardly-recessed cavity of the upper mold. A molding compound is injected into the upwardly-recessed cavity to form a dam on the peripheral portion of the substrate. Then the upper and lower molds and the interposer are removed from the substrate to expose area covered by the interposer on the substrate. At least one photosensitive chip is mounted on the exposed area of the substrate. A lid seals the dam such that the chip is received in a space defined by the substrate, the dam and the lid.
摘要翻译： 提供了具有感光芯片的半导体封装的制造方法。 制备具有芯的衬底。 插入器安装在衬底上，衬底的周边部分从插入件露出。 进行成型工艺，并且将基板夹在上模具和下模具之间，其中插入件容纳在上模具的向上凹入的空腔中。 将模塑料注入到上凹腔中以在基材的周边部分上形成坝。 然后将上模和下模和插入件从基板上移除以露出基板上由插入件覆盖的区域。 至少一个感光芯片安装在基板的暴露区域上。 盖子密封大坝，使得芯片被容纳在由基板，坝和盖子限定的空间中。
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公开(公告)号：USD492314S1
公开(公告)日：2004-06-29
申请号：US29192300
申请日：2003-10-21
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37.发明授权公开(公告)号：US07679178B2
公开(公告)日：2010-03-16
申请号：US11974441
申请日：2007-10-12
申请人： Han-Ping Pu , Chien-Ping Huang , Chih-Ming Huang , Yu-Po Wang , Cheng-Hsu Hsiao
发明人： Han-Ping Pu , Chien-Ping Huang , Chih-Ming Huang , Yu-Po Wang , Cheng-Hsu Hsiao
IPC分类号： H01L23/02
CPC分类号： H01L21/568 , H01L23/3128 , H01L24/16 , H01L24/45 , H01L24/48 , H01L24/73 , H01L25/105 , H01L2224/0554 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/16145 , H01L2224/16225 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/00014 , H01L2924/01079 , H01L2924/15192 , H01L2924/15311 , H01L2924/16151 , H01L2924/16195 , H01L2924/18161 , H01L2924/19107 , H01L2924/00012 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A semiconductor package on which a semiconductor device can be stacked and fabrication method thereof are provided. The fabrication method includes the steps of mounting and electrically connecting at least one semiconductor chip on the substrate, mounting an electrical connecting structure consisting of an upper layer circuit board and a lower layer circuit board on the substrate and electrically connecting the electrical connecting structure to the substrate, where the semiconductor chip is received in a receiving space formed in the electrical connecting structure; forming an encapsulant on the substrate encapsulating the semiconductor chip and the electrical connecting structure, and after the encapsulant is formed, exposing top surface of the upper layer circuit board with a plurality of solder pads from the encapsulant to allow at least one semiconductor device to electrically connect the upper layer circuit board so as to form a stack structure.
摘要翻译： 提供半导体器件可堆叠的半导体封装件及其制造方法。 该制造方法包括以下步骤：在基板上安装和电连接至少一个半导体芯片，将由上层电路板和下层电路板组成的电连接结构安装在基板上，并将电连接结构电连接到 衬底，其中所述半导体芯片被容纳在形成在所述电连接结构中的接收空间中; 在封装半导体芯片和电连接结构的基板上形成密封剂，并且在形成密封剂之后，用来自密封剂的多个焊盘将上层电路板的顶表面曝光，以允许至少一个半导体器件电 连接上层电路板，形成堆叠结构。
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公开(公告)号：US20070278701A1
公开(公告)日：2007-12-06
申请号：US11591800
申请日：2006-11-01
IPC分类号： H01L23/28
CPC分类号： H01L21/561 , H01L21/481 , H01L23/3121 , H01L23/49805 , H01L23/49811 , H01L24/48 , H01L24/97 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/97 , H01L2924/00014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/181 , H01L2224/85 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package and a method for fabricating the same are disclosed. The method includes installing a plurality of conductive components on a plurality of chip carriers of a chip carrier module, connecting electrically the conductive components to electrical connection points of the adjacent chip carriers, mounting and electrically connecting a semiconductor chip to each of the chip carries, forming an encapsulant for enveloping the semiconductor chip and the conductive components, cutting the chip carriers to separate the conductive components installed thereon, exposing a portion of the conductive components out of the encapsulant, forming on the exposed portion of the conductive components an electroplated layer of nickel/gold, and separating the chip carriers from each other. The conductive components exposed out of the encapsulant provide extra electrical connection points and thereby promote the functionalities of electronic products.
摘要翻译： 公开了一种半导体封装及其制造方法。 该方法包括在芯片载体模块的多个芯片载体上安装多个导电组件，将导电组件电连接到相邻芯片载体的电连接点，将半导体芯片安装并电连接到每个芯片载体， 形成用于包封半导体芯片和导电部件的密封剂，切割芯片载体以分离安装在其上的导电组件，将一部分导电组分暴露于密封剂外，在导电组件的暴露部分上形成电镀层 镍/金，并且将芯片载体彼此分离。 从密封剂露出的导电组件提供额外的电连接点，从而促进电子产品的功能。
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39.发明授权Wafer level semiconductor package with build-up layer and method for fabricating the same 有权具有积层的晶片级半导体封装及其制造方法公开(公告)号：US07170152B2
公开(公告)日：2007-01-30
申请号：US10846460
申请日：2004-05-14
IPC分类号： H01L23/02
CPC分类号： H01L21/6835 , H01L21/568 , H01L24/19 , H01L24/96 , H01L24/97 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/19 , H01L2224/20 , H01L2224/32225 , H01L2224/32245 , H01L2224/73267 , H01L2224/97 , H01L2924/01029 , H01L2924/01033 , H01L2924/12042 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , H01L2924/351 , H01L2924/3511 , H01L2224/82 , H01L2924/00
摘要： A wafer level semiconductor package with a build-up layer is provided, which includes a glass frame having a through hole for receiving a semiconductor chip therein, a low-modulus buffer material filled within the space formed between the semiconductor chip and the glass frame, a build-up layer formed on the glass frame and the semiconductor chip such that the build-up layer is electrically connected to the semiconductor chip, and a plurality of conductive elements mounted on the build-up layer so that the semiconductor chip is electrically connected to external devices. With the use of the glass frame and low-modulus buffer material, the wafer level semiconductor package thus-obtained is free from warpage, chip-crack, and delamination problems and the reliability thereof is enhanced. A method for fabricating the wafer level semiconductor package is also provided.
摘要翻译： 提供具有积层的晶片级半导体封装，其包括具有用于接收其中的半导体芯片的通孔的玻璃框架，填充在形成在半导体芯片和玻璃框架之间的空间内的低模量缓冲材料， 形成在所述玻璃框架和所述半导体芯片上的堆积层，使得所述积层层电连接到所述半导体芯片，以及安装在所述积层层上的多个导电元件，使得所述半导体芯片电连接 到外部设备。 通过使用玻璃框架和低模量缓冲材料，由此获得的晶片级半导体封装没有翘曲，芯片裂纹和分层问题，并且其可靠性得到提高。 还提供了一种用于制造晶片级半导体封装的方法。
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40.发明授权公开(公告)号：US07005720B2
公开(公告)日：2006-02-28
申请号：US10763656
申请日：2004-01-23
CPC分类号： H01L31/0203 , H01L27/14618 , H01L2224/04042 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/15311 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor package with a photosensitive chip and a fabrication method thereof are provided. A substrate having a core is prepared. A solder mask layer is applied over a surface of the core and formed with an opening to expose a continuous peripheral portion on the surface of the core. At least one photosensitive chip is mounted on and electrically connected to the substrate. An encapsulation dam is formed on the continuous peripheral portion of the core and surrounds the chip. The dam includes a shoulder portion adjacent to and flush with the solder mask layer, and a protruded support portion surrounding the shoulder portion. A lid is attached to the support portion of the dam for sealing the dam such that the chip is received in a space defined by the substrate, the dam and the lid.
摘要翻译： 提供具有感光芯片的半导体封装及其制造方法。 制备具有芯的衬底。 将焊接掩模层施加在芯的表面上并形成有开口以暴露芯的表面上的连续周边部分。 至少一个感光芯片安装在基板上并与其电连接。 在芯的连续外围部分上形成封装坝，并围绕芯片。 大坝包括与焊料掩模层相邻并与其齐平的肩部，以及围绕肩部的突出的支撑部。 盖子附接到坝的支撑部分，用于密封坝，使得芯片被容纳在由基板，坝和盖子限定的空间中。
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