利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

48 条记录 (耗时 0.039 秒)

    Raised base bipolar transistor structure and its method of fabrication
    32.
    发明授权
    Raised base bipolar transistor structure and its method of fabrication 失效
    基极双极晶体管结构及其制作方法

    公开(公告)号：US5017990A

    公开(公告)日：1991-05-21

    申请号：US445251

    申请日：1989-12-01

    申请人： Tze-Chiang Chen ,  Ching-Te Kent Chuang ,  Guann-Pyng Li ,  Tak Hung Ning

    发明人： Tze-Chiang Chen ,  Ching-Te Kent Chuang ,  Guann-Pyng Li ,  Tak Hung Ning

    IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L29/10 ,  H01L29/732

    CPC分类号： H01L29/66287 ,  H01L29/1004 ,  H01L29/732

    摘要： The invention relates to a bipolar transistor structure which includes a layer of semiconductor material having a single crystal raised base, a single crystal or polycrystalline emitter and adjacent polycrystalline regions which provide an electrical connection to the emitter. The invention also relates to the method of fabricating such a structure and includes the step of depositing a conformal layer of semiconductor material of one conductivity type over a region of opposite conductivity and over insulation such that single crystal and polycrystalline regions form over single crystal material and insulation, respectively. In a subsequent step, a layer of opposite conductivity type semiconductor material is deposited on the first layer forming single crystal or polycrystalline material over single crystal and polycrystalline material over polycrystalline. Then, in a final step, the structure is subjected to an out-diffusion step which simultaneously forms a single crystal emitter region of opposite conductivity type, a p-n junction in the one conductivity type single crystal region and regions of opposite conductivity type which act as an interconnection to the emitter region.

    Interface structure for channel mobility improvement in high-k metal gate stack
    34.
    发明授权
    Interface structure for channel mobility improvement in high-k metal gate stack 有权
    高k金属栅极堆叠中沟道迁移率改善的接口结构

    公开(公告)号：US08492852B2

    公开(公告)日：2013-07-23

    申请号：US12792242

    申请日：2010-06-02

    申请人： Tze-Chiang Chen ,  Dechao Guo ,  Philip J. Oldiges ,  Yanfeng Wang

    发明人： Tze-Chiang Chen ,  Dechao Guo ,  Philip J. Oldiges ,  Yanfeng Wang

    IPC分类号： H01L21/02 ,  H01L21/31 ,  H01L21/469

    CPC分类号： H01L29/517 ,  H01L21/28176 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/51 ,  H01L29/513 ,  H01L29/518

    摘要： A gate stack structure for field effect transistor (FET) devices includes a nitrogen rich first dielectric layer formed over a semiconductor substrate surface; a nitrogen deficient, oxygen rich second dielectric layer formed on the nitrogen rich first dielectric layer, the first and second dielectric layers forming, in combination, a bi-layer interfacial layer; a high-k dielectric layer formed over the bi-layer interfacial layer; a metal gate conductor layer formed over the high-k dielectric layer; and a work function adjusting dopant species diffused within the high-k dielectric layer and within the nitrogen deficient, oxygen rich second dielectric layer, and wherein the nitrogen rich first dielectric layer serves to separate the work function adjusting dopant species from the semiconductor substrate surface.

    摘要翻译： 用于场效应晶体管（FET）器件的栅极堆叠结构包括形成在半导体衬底表面上的富氮第一介电层; 形成在富氮第一介电层上的缺氮富氧的第二电介质层，第一和第二电介质层组合形成双层界面层; 形成在双层界面层上的高k电介质层; 形成在高k电介质层上的金属栅极导体层; 以及调节掺杂物质的功函数，其在所述高k电介质层内和所述缺氮富氧的第二电介质层内扩散，并且其中所述富氮第一介电层用于将所述功函数调节掺杂剂物质与所述半导体衬底表面分离。

    Ultrathin buried insulators in Si or Si-containing material
    36.
    发明申请
    Ultrathin buried insulators in Si or Si-containing material 审中-公开
    超薄绝缘子在Si或含Si材料中

    公开(公告)号：US20060105559A1

    公开(公告)日：2006-05-18

    申请号：US10990300

    申请日：2004-11-15

    申请人： Tze-Chiang Chen ,  Bernard Meyerson ,  Devendra Sadana

    发明人： Tze-Chiang Chen ,  Bernard Meyerson ,  Devendra Sadana

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76243 ,  H01L21/31662

    摘要： A method for forming an ultra thin buried oxide layer is described incorporating the steps of forming a first epitaxial layer containing Si on a Si containing substrate having a thickness from about 10 to about 300 angstroms thick, forming a second epitaxial layer containing Si having a thickness from about 100 angstroms to about 1 micron and annealing the substrate at a temperature from 1200° C. to 1400°0 C. in an oxygen containing atmosphere. The invention over comes the problem of the buried oxide breaking up into oxide islands during the anneal.

    摘要翻译： 描述了一种用于形成超薄掩埋氧化物层的方法，其包括以下步骤：在厚度约10至约300埃厚的含硅衬底上形成含有Si的第一外延层，形成含有Si厚度的第二外延层 从约100埃至约1微米，并在含氧气氛中在1200℃至1400℃的温度下退火底物。 本发明是在退火期间埋入氧化物分解成氧化物岛的问题。

    Crack stops
    37.
    发明授权
    Crack stops 失效
    裂缝停止

    公开(公告)号：US6025639A

    公开(公告)日：2000-02-15

    申请号：US61538

    申请日：1998-04-16

    申请人： Alexander R. Mitwalsky ,  Tze-Chiang Chen

    发明人： Alexander R. Mitwalsky ,  Tze-Chiang Chen

    IPC分类号： H01L21/301 ,  H01L21/78 ,  H01L23/544

    CPC分类号： H01L21/78

    摘要： Crack stops for substantially preventing cracks and chips produced along the dicing channel from spreading into the active areas of the ICs are described. The crack stops are formed by creating discontinuities in the thickness of the dielectric layer in the dicing channel near the chip edges. The discontinuities can result in increasing and/or decreasing the thickness of the dielectric layer.

    摘要翻译： 描述了用于基本上防止沿着切割通道产生的裂纹的裂纹停止扩散到IC的有源区域。 通过在芯片边缘附近的切割通道中的介电层的厚度产生不连续性来形成裂纹停止。 不连续性可导致电介质层的厚度增加和/或减小。

    Crack stops
    38.
    发明授权
    Crack stops 失效

    公开(公告)号：US5789302A

    公开(公告)日：1998-08-04

    申请号：US823668

    申请日：1997-03-24

    申请人： Alexander R. Mitwalsky ,  Tze-Chiang Chen

    发明人： Alexander R. Mitwalsky ,  Tze-Chiang Chen

    IPC分类号： H01L21/301 ,  H01L21/78 ,  H01L21/46

    CPC分类号： H01L21/78

    摘要： Crack stops for substantially preventing cracks and chips produced along the dicing channel from spreading into the active areas of the ICs are described. The crack stops are formed by creating discontinuities in the thickness of the dielectric layer in the dicing channel near the chip edges. The discontinuities can result in increasing and/or decreasing the thickness of the dielectric layer.

    Semiconductor-on-insulator (SOI) substrates with ultra-thin SOI layers and buried oxides
    39.
    发明授权
    Semiconductor-on-insulator (SOI) substrates with ultra-thin SOI layers and buried oxides 有权
    具有超薄SOI层和掩埋氧化物的绝缘体上半导体（SOI）衬底

    公开(公告)号：US09059245B2

    公开(公告)日：2015-06-16

    申请号：US13483781

    申请日：2012-05-30

    申请人： Tze-Chiang Chen ,  Joel P. de Souza ,  Devendra K. Sadana ,  Ghavam G. Shahidi

    发明人： Tze-Chiang Chen ,  Joel P. de Souza ,  Devendra K. Sadana ,  Ghavam G. Shahidi

    IPC分类号： H01L21/76 ,  H01L21/762

    CPC分类号： H01L21/76243

    摘要： Semiconductor-on-insulator (SOI) substrates including a buried oxide (BOX) layer having a thickness of less than 300 Å are provided. The (SOI) substrates having the thin BOX layer are provided using a method including a step in which oxygen ions are implanted at high substrate temperatures (greater than 600° C.), and at a low implant energy (less than 40 keV). An anneal step in an oxidizing atmosphere follows the implant step and is performed at a temperature less than 1250° C. The anneal step in oxygen containing atmosphere converts the region containing implanted oxygen atoms formed by the implant step into a BOX having a thickness of less than 300 Å. In some instances, the top semiconductor layer of the SOI substrate has a thickness of less than 300 Å.

    摘要翻译： 提供了包括厚度小于300埃的掩埋氧化物（BOX）层的绝缘体上半导体（SOI）衬底。 使用包括以高衬底温度（大于600℃）和低注入能量（小于40keV）注入氧离子的步骤的方法提供具有薄BOX层的（SOI）衬底。 氧化气氛中的退火步骤遵循注入步骤，并且在低于1250℃的温度下进行。含氧气氛中的退火步骤将包含由注入步骤形成的注入的氧原子的区域转换成厚度较小的BOX 比300Å。 在一些情况下，SOI衬底的顶部半导体层具有小于300埃的厚度。

    SEMICONDUCTOR-ON-INSULATOR (SOI) SUBSTRATES WITH ULTRA-THIN SOI LAYERS AND BURIED OXIDES
    40.
    发明申请
    SEMICONDUCTOR-ON-INSULATOR (SOI) SUBSTRATES WITH ULTRA-THIN SOI LAYERS AND BURIED OXIDES 有权
    半导体绝缘体（SOI）衬底，具有超薄SOI层和铜氧化物

    公开(公告)号：US20130320483A1

    公开(公告)日：2013-12-05

    申请号：US13483781

    申请日：2012-05-30

    申请人： Tze-Chiang Chen ,  Joel P. de Souza ,  Devendra K. Sadana ,  Ghavam G. Shahidi

    发明人： Tze-Chiang Chen ,  Joel P. de Souza ,  Devendra K. Sadana ,  Ghavam G. Shahidi

    IPC分类号： H01L21/762 ,  H01L29/02

    CPC分类号： H01L21/76243

    摘要： Semiconductor-on-insulator (SOI) substrates including a buried oxide (BOX) layer having a thickness of less than 300 Å are provided. The (SOI) substrates having the thin BOX layer are provided using a method including a step in which oxygen ions are implanted at high substrate temperatures (greater than 600° C.), and at a low implant energy (less than 40 keV). An anneal step in an oxidizing atmosphere follows the implant step and is performed at a temperature less than 1250° C. The anneal step in oxygen containing atmosphere converts the region containing implanted oxygen atoms formed by the implant step into a BOX having a thickness of less than 300 Å. In some instances, the top semiconductor layer of the SOI substrate has a thickness of less than 300 Å.

    摘要翻译： 提供了包括厚度小于300埃的掩埋氧化物（BOX）层的绝缘体上半导体（SOI）衬底。 使用包括以高衬底温度（大于600℃）和低注入能量（小于40keV）注入氧离子的步骤的方法提供具有薄BOX层的（SOI）衬底。 氧化气氛中的退火步骤遵循注入步骤，并且在低于1250℃的温度下进行。含氧气氛中的退火步骤将包含由注入步骤形成的注入的氧原子的区域转换成厚度较小的BOX 比300Å。 在一些情况下，SOI衬底的顶部半导体层具有小于300埃的厚度。