公开(公告)号：US09966266B2

公开(公告)日：2018-05-08

申请号：US15137010

申请日：2016-04-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ying Lin ,  Chueh-Yang Liu ,  Yu-Ren Wang ,  Chun-Wei Yu ,  Kuang-Hsiu Chen ,  Yi-Liang Ye ,  Hsu Ting ,  Neng-Hui Yang

IPC: H01L21/02 ,  H01L21/268 ,  H01L21/67 ,  H01L21/265 ,  H01L21/3065 ,  H01L21/306 ,  H01L21/687 ,  H01L29/66

CPC classification number: H01L21/2686 ,  H01L21/02057 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/67051 ,  H01L21/6708 ,  H01L21/67115 ,  H01L21/68785 ,  H01L29/0847 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/7834

Abstract: An apparatus for semiconductor wafer treatment includes a wafer holding unit configured to receive a single wafer, at least a solution supply unit configured to apply a solution onto the wafer and an irradiation unit configured to emit irradiation to the wafer. The irradiation unit further includes at least a plurality of first light sources configured to emit irradiation in FIR range and a plurality of second light sources configured to emit irradiation in UV range.

公开(公告)号：US09646889B1

公开(公告)日：2017-05-09

申请号：US15003782

申请日：2016-01-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Wei Yu ,  Hsu Ting ,  Chueh-Yang Liu ,  Yu-Ren Wang ,  Kuang-Hsiu Chen

IPC: H01L21/02 ,  H01L21/033 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/08 ,  H01L29/24 ,  H01L29/267 ,  H01L29/161 ,  H01L29/165 ,  H01L29/78 ,  H01L23/535

CPC classification number: H01L29/7845 ,  H01L21/02065 ,  H01L21/28123 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823871 ,  H01L23/535 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/45 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first gate structure on the substrate and a first spacer adjacent to the first gate structure; forming a first epitaxial layer in the substrate adjacent to the first gate structure; forming a first hard mask layer on the first gate structure; removing part of the first hard mask layer to form a protective layer on the first epitaxial layer; and removing the remaining first hard mask layer.

公开(公告)号：US20250089334A1

公开(公告)日：2025-03-13

申请号：US18379674

申请日：2023-10-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Fan Li ,  Chen-Ming Wang ,  Po-Ching Su ,  Pei-Hsun Kao ,  Ti-Bin Chen ,  Chun-Wei Yu ,  Chih-Chiang Wu

IPC: H01L29/417 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor includes a substrate. A gate structure is disposed on the substrate. A liner oxide contacts a side of the gate structure. A silicon oxide spacer contacts the liner oxide. An end of the silicon oxide spacer forms a kink profile. A silicon nitride spacer contacts the silicon oxide spacer and a tail of the silicon nitride spacer covers part of the kink profile. A stressor covers the silicon nitride spacer and the substrate.

公开(公告)号：US11735661B2

公开(公告)日：2023-08-22

申请号：US17330443

申请日：2021-05-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuang-Hsiu Chen ,  Sung-Yuan Tsai ,  Chi-Hsuan Tang ,  Chun-Wei Yu ,  Yu-Ren Wang

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/36 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/7848 ,  H01L29/0847 ,  H01L29/36 ,  H01L29/42364 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66575

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure and an epitaxial structure. The gate structure is disposed on the substrate, and the epitaxial structure is disposed in the substrate, at one side of the gate structure. The epitaxial structure includes a portion being protruded from a top surface of the substrate, and the portion includes a discontinuous sidewall, with a distance between a turning point of the discontinuous sidewalls and the gate structure being a greatest distance between the epitaxial structure and the gate structure.

公开(公告)号：US11049971B2

公开(公告)日：2021-06-29

申请号：US16205233

申请日：2018-11-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuang-Hsiu Chen ,  Sung-Yuan Tsai ,  Chi-Hsuan Tang ,  Chun-Wei Yu ,  Yu-Ren Wang

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/36 ,  H01L29/66 ,  H01L29/423

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure and an epitaxial structure. The gate structure is disposed on the substrate, and the epitaxial structure is disposed in the substrate, at one side of the gate structure. The epitaxial structure includes a portion being protruded from a top surface of the substrate, and the portion includes a discontinuous sidewall, with a distance between a turning point of the discontinuous sidewalls and the gate structure being a greatest distance between the epitaxial structure and the gate structure.

公开(公告)号：US10651174B2

公开(公告)日：2020-05-12

申请号：US16412337

申请日：2019-05-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Liang Ye ,  Kuang-Hsiu Chen ,  Chun-Wei Yu ,  Chueh-Yang Liu ,  Yu-Ren Wang

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/51

Abstract: A method of forming a gate structure on a fin structure includes the steps of providing a fin structure covered by a first silicon oxide layer, a silicon nitride layer, a gate material and a cap material in sequence, wherein the silicon nitride layer contacts the first silicon oxide layer. Later, the cap material is patterned to form a first cap layer and the gate material is patterned to form a first gate electrode by taking the silicon nitride layer as an etching stop layer. Then, the silicon nitride layer not covered by the first gate electrode is removed to expose part of the first silicon oxide layer. Finally, a first dielectric layer is formed to conformally cover the first silicon oxide layer, the first gate electrode and the first cap layer.

公开(公告)号：US10446667B2

公开(公告)日：2019-10-15

申请号：US16404749

申请日：2019-05-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Ying Lin ,  Yi-Liang Ye ,  Sung-Yuan Tsai ,  Chun-Wei Yu ,  Yu-Ren Wang ,  Zhen Wu ,  Tai-Yen Lin

IPC: H01L21/00 ,  H01L29/66 ,  H01L21/768 ,  H01L21/3065 ,  H01L21/306 ,  H01L21/285 ,  H01L29/78 ,  H01L21/265 ,  H01L29/08 ,  H01L21/02 ,  H01L21/3115

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first gate structure on a substrate; performing a first etching process to form a recess adjacent to the first gate structure; performing an ion implantation process to form an amorphous layer directly under the recess; performing a second etching process to remove the amorphous layer; and forming an epitaxial layer in the recess.

公开(公告)号：US20190279979A1

公开(公告)日：2019-09-12

申请号：US16412337

申请日：2019-05-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yi-Liang Ye ,  Kuang-Hsiu Chen ,  Chun-Wei Yu ,  Chueh-Yang Liu ,  Yu-Ren Wang

IPC: H01L27/088 ,  H01L21/8234

Abstract: A method of forming a gate structure on a fin structure includes the steps of providing a fin structure covered by a first silicon oxide layer, a silicon nitride layer, a gate material and a cap material in sequence, wherein the silicon nitride layer contacts the first silicon oxide layer. Later, the cap material is patterned to form a first cap layer and the gate material is patterned to form a first gate electrode by taking the silicon nitride layer as an etching stop layer. Then, the silicon nitride layer not covered by the first gate electrode is removed to expose part of the first silicon oxide layer. Finally, a first dielectric layer is formed to conformally cover the first silicon oxide layer, the first gate electrode and the first cap layer.

公开(公告)号：US10332750B2

公开(公告)日：2019-06-25

申请号：US15820443

申请日：2017-11-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuang-Hsiu Chen ,  Hsu Ting ,  Chung-Fu Chang ,  Shi-You Liu ,  Chun-Wei Yu ,  Yu-Ren Wang

IPC: H01L21/3105 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L29/165 ,  H01L21/266 ,  H01L21/324 ,  H01L29/08

Abstract: A method for fabricating a semiconductor device. A gate is formed on a substrate. A spacer is formed on each sidewall of the gate. A hard mask layer is formed on the spacer. A recessed region is formed in the substrate and adjacent to the hard mask layer. An epitaxial layer is formed in the recessed region. The substrate is subjected to an ion implantation process to bombard particle defects on the hard mask layer with inert gas ions. An annealing process is performed to repair damages to the epitaxial layer caused by the ion implantation process. The hard mask layer is then removed.

公开(公告)号：US10079143B2

公开(公告)日：2018-09-18

申请号：US15636660

申请日：2017-06-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsu Ting ,  Chun-Wei Yu ,  Chueh-Yang Liu ,  Yu-Ren Wang

IPC: H01L21/02 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L21/311

CPC classification number: H01L21/0206 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0657

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes fin shaped structures and a recessed insulating layer. The fin shaped structures are disposed on a substrate. The recessed insulating layer covers a bottom portion of each of the fin shaped structures to expose a top portion of each of the fin shaped structures. The recessed insulating layer has a curve surface and a wicking structure is defined between a peak and a bottom of the curve surface. The wicking structure is disposed between the fin shaped structures and has a height being about 1/12 to 1/10 of a height of the top portion of the fin shaped structures.