公开(公告)号：US09892283B2

公开(公告)日：2018-02-13

申请号：US14884502

申请日：2015-10-15

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Terry Parks ,  Brent Bean ,  Thomas A. Crispin

IPC: G06F21/72 ,  G06F9/30 ,  H04L9/08 ,  G06F21/74 ,  G06F12/0875 ,  G06F21/52 ,  G06F21/60 ,  G06F21/71 ,  H04L9/06

CPC classification number: G06F21/72 ,  G06F9/30003 ,  G06F9/30079 ,  G06F9/30178 ,  G06F9/30189 ,  G06F12/0875 ,  G06F21/52 ,  G06F21/602 ,  G06F21/71 ,  G06F21/74 ,  G06F2212/402 ,  G06F2212/452 ,  G06F2221/2107 ,  H04L9/0618 ,  H04L9/0861 ,  H04L9/0891 ,  H04L9/0894 ,  H04L2209/12 ,  H04L2209/20

Abstract: A microprocessor and method are provided for securely decrypting and executing encrypted instructions within a microprocessor. A plurality of master keys are stored in a secure memory. Encrypted instructions are fetched from an instruction cache. A set of one or more master keys are selected from the secure memory based upon an encrypted instruction fetch address. The selected set of master keys or a decryption key derived therefrom is used to decrypt the encrypted instructions fetched from the instruction cache. The decrypted instructions are then securely executed within the microprocessor. In one implementation, the master keys are intervolved with each other to produce a new decryption key with every fetch quantum. Moreover, a new set of master keys is selected with every new block of instructions.

公开(公告)号：US09830155B2

公开(公告)日：2017-11-28

申请号：US15140010

申请日：2016-04-27

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Terry Parks ,  Brent Bean

IPC: G06F9/30 ,  G06F9/28 ,  G06F9/32 ,  G06F9/38

CPC classification number: G06F9/30178 ,  G06F9/26 ,  G06F9/268 ,  G06F9/28 ,  G06F9/30145 ,  G06F9/32 ,  G06F9/3802

Abstract: A microprocessor includes compressed and uncompressed microcode memory storages, having N-bit wide and M-bit wide addressable words, respectively, where N

公开(公告)号：US09588845B2

公开(公告)日：2017-03-07

申请号：US14522520

申请日：2014-10-23

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Terry Parks ,  Rodney E. Hooker

IPC: G06F11/14 ,  G06F11/07 ,  G06F9/38

CPC classification number: G06F11/1446 ,  G06F9/30014 ,  G06F9/30185 ,  G06F9/38 ,  G06F9/3863 ,  G06F11/0754 ,  G06F11/0793 ,  G06F11/1402 ,  G06F11/1435 ,  G06F2201/84

Abstract: A processor includes a storage configured to receive a snapshot of a state of the processor prior to performing a set of computations in an approximating manner. The processor also includes an indicator that indicates an amount of error accumulated while the set of computations is performed in the approximating manner. When the processor detects that the amount of error accumulated has exceeded an error bound, the processor is configured to restore the state of the processor to the snapshot from the storage.

Abstract translation: 处理器包括被配置为在以近似方式执行一组计算之前接收处理器的状态的快照的存储器。 处理器还包括指示器，其指示在以近似方式执行计算集合时累积的误差量。 当处理器检测到累积的错误量超过了错误限制时，处理器被配置为将处理器的状态从存储恢复到快照。

公开(公告)号：US09507597B2

公开(公告)日：2016-11-29

申请号：US14165354

申请日：2014-01-27

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Rodney E. Hooker ,  Terry Parks ,  John Michael Greer

IPC: G06F9/00 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30058 ,  G06F9/3848 ,  G06F9/3851

Abstract: A microprocessor includes a predicting unit and a control unit. The control unit controls the predicting unit to accumulate a history of characteristics of executed instructions and makes predictions related to subsequent instructions based on the history while the microprocessor is running a first thread. The control unit also detects a transition from running the first thread to running a second thread and controls the predicting unit to selectively suspend accumulating the history and making the predictions using the history while running the second thread. The predicting unit makes static predictions while running the second thread. The selectivity may be based on the privilege level, identity or length of the second thread, static prediction effectiveness during a previous execution instance of the thread, whether the transition was made due to a system call, and whether the second thread is an interrupt handler.

Abstract translation: 微处理器包括预测单元和控制单元。 控制单元控制预测单元累积执行指令的特征历史，并且在微处理器运行第一线程的同时基于历史来进行与后续指令相关的预测。 控制单元还检测从运行第一线程到运行第二线程的转变，并且控制预测单元选择性地暂停累积历史并且在运行第二线程时使用历史进行预测。 预测单元在运行第二个线程时进行静态预测。 选择性可以基于第二线程的特权级别，身份或长度，线程的先前执行实例期间的静态预测有效性，是否由于系统调用而进行转换，以及第二线程是否是中断处理程序 。

公开(公告)号：US09507404B2

公开(公告)日：2016-11-29

申请号：US14281621

申请日：2014-05-19

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Terry Parks ,  Brent Bean ,  Stephan Gaskins

IPC: G06F1/00 ,  G06F1/32 ,  G06F12/08 ,  G06F13/24 ,  G06F9/38 ,  G06F9/30 ,  G06F9/44 ,  G06F1/04 ,  G06F1/12

CPC classification number: G06F9/3885 ,  G06F1/04 ,  G06F1/12 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/30032 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/30087 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3861 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4411 ,  G06F9/4418 ,  G06F12/0808 ,  G06F12/084 ,  G06F12/0875 ,  G06F13/24 ,  G06F13/364 ,  G06F13/42 ,  G06F21/53 ,  G06F21/57 ,  G06F2212/452 ,  G06F2212/6028 ,  G06F2212/62 ,  H01L22/34 ,  H04L9/0877 ,  H04L9/0897 ,  Y02B70/12 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/30 ,  Y02D10/10 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/13 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/30 ,  Y02D50/20

Abstract: A microprocessor includes a plurality of cores, a shared cache memory, and a control unit that individually puts each core to sleep by stopping its clock signal. Each core executes a sleep instruction and responsively makes a respective request of the control unit to put the core to sleep, which the control unit responsively does, and detects when all the cores have made the respective request and responsively wakes up only the last requesting cores. The last core writes back and invalidates the shared cache memory and indicates it has been invalidated and makes a request to the control unit to put the last core back to sleep. The control unit puts the last core back to sleep and continuously keeps the other cores asleep while the last core writes back and invalidates the shared cache memory, indicates the shared cache memory was invalidated, and is put back to sleep.

Abstract translation: 微处理器包括多个核心，共享高速缓冲存储器和控制单元，其通过停止其时钟信号来单独地将每个核心置于睡眠状态。 每个核心执行睡眠指令，并且响应地使控制单元的相应请求将核心置于睡眠状态，控制单元响应地进行该操作，并且检测所有核心何时完成了各自的请求，并且响应地只唤醒最后请求的核心 。 最后一个内核写回并使共享高速缓存内存无效，并指示它已被无效，并向控制单元发出请求以使最后一个核心返回休眠状态。 控制单元将最后一个核心置于休眠状态，并持续保持其他内核处于睡眠状态，同时最后一个内核回写并使共享缓存内存无效，表示共享高速缓存内存无效，并返回睡眠状态。

公开(公告)号：US09372696B2

公开(公告)日：2016-06-21

申请号：US14088620

申请日：2013-11-25

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. Glenn Henry ,  Terry Parks ,  Brent Bean

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38

CPC classification number: G06F9/30145 ,  G06F9/30178 ,  G06F9/328 ,  G06F9/3891

Abstract: A microprocessor includes a plurality of memories each configured to hold microcode instructions. At least a first of the plurality of memories is configured to provide M-bit wide words of compressed microcode instructions, and at least a second of the plurality of memories is configured to provide N-bit wide words of uncompressed microcode instructions. M and N are integers greater than zero and N is greater than M. The microprocessor also includes a decompression unit configured to decompress the compressed microcode instructions after being fetched from the at least a first of the plurality of memories and before being executed.

Abstract translation: 微处理器包括多个存储器，每个存储器被配置为保持微码指令。 所述多个存储器中的至少第一个被配置为提供压缩微码指令的M位宽的字，并且所述多个存储器中的至少一个存储器被配置为提供未压缩的微代码指令的N位宽字。 M和N是大于零并且N大于M的整数。微处理器还包括解压缩单元，其被配置为在从多个存储器中的至少第一个存储器中取出并在执行之前解压缩压缩的微代码指令。

公开(公告)号：US20150089142A1

公开(公告)日：2015-03-26

申请号：US14050757

申请日：2013-10-10

Applicant: VIA Technologies, Inc.

Inventor： Terry Parks

IPC: G06F12/08 ,  G06F9/38

CPC classification number: G06F12/0875 ,  G06F9/30076 ,  G06F9/30079 ,  G06F9/38 ,  G06F9/3867 ,  G06F9/3897 ,  G06F9/44505

Abstract: A microprocessor includes an instruction cache and a hardware state machine configured to detect a continuous sequence of N no operation (NOP) instructions within a stream of instruction bytes fetched from the instruction cache, wherein N is greater than zero. The microprocessor is configured to suspend fetching and executing instructions from the instruction cache in response to detecting the continuous sequence of N NOP instructions.

Abstract translation: 微处理器包括指令高速缓存和配置成检测从指令高速缓存取出的指令字节流内的N个无操作（NOP）指令的连续序列的硬件状态机，其中N大于零。 响应于检测到N NOP指令的连续序列，微处理器被配置为暂停从指令高速缓存取出和执行指令。

公开(公告)号：US20150067214A1

公开(公告)日：2015-03-05

申请号：US14281621

申请日：2014-05-19

Applicant: VIA Technologies, Inc.

Inventor： G. Glenn Henry ,  Terry Parks ,  Brent Bean ,  Stephan Gaskins

IPC: G06F1/32 ,  G06F13/24 ,  G06F12/08

CPC classification number: G06F9/3885 ,  G06F1/04 ,  G06F1/12 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/30032 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/30087 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3861 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4411 ,  G06F9/4418 ,  G06F12/0808 ,  G06F12/084 ,  G06F12/0875 ,  G06F13/24 ,  G06F13/364 ,  G06F13/42 ,  G06F21/53 ,  G06F21/57 ,  G06F2212/452 ,  G06F2212/6028 ,  G06F2212/62 ,  H01L22/34 ,  H04L9/0877 ,  H04L9/0897 ,  Y02B70/12 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/30 ,  Y02D10/10 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/13 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/30 ,  Y02D50/20

Abstract: A microprocessor includes a plurality of cores, a shared cache memory, and a control unit that individually puts each core to sleep by stopping its clock signal. Each core executes a sleep instruction and responsively makes a respective request of the control unit to put the core to sleep, which the control unit responsively does, and detects when all the cores have made the respective request and responsively wakes up only the last requesting cores. The last core writes back and invalidates the shared cache memory and indicates it has been invalidated and makes a request to the control unit to put the last core back to sleep. The control unit puts the last core back to sleep and continuously keeps the other cores asleep while the last core writes back and invalidates the shared cache memory, indicates the shared cache memory was invalidated, and is put back to sleep.

Abstract translation: 微处理器包括多个核心，共享高速缓冲存储器和控制单元，其通过停止其时钟信号来单独地将每个核心置于睡眠状态。 每个核心执行睡眠指令，并且响应地使控制单元的相应请求将核心置于睡眠状态，控制单元响应地进行该操作，并且检测所有核心何时完成了各自的请求，并且响应地只唤醒最后请求的核心 。 最后一个内核写回并使共享高速缓存内存无效，并指示它已被无效，并向控制单元发出请求以使最后一个核心返回休眠状态。 控制单元将最后一个核心置于休眠状态，并持续保持其他内核处于睡眠状态，同时最后一个内核回写并使共享缓存内存无效，表示共享高速缓存内存无效，并返回睡眠状态。

公开(公告)号：US20140365753A1

公开(公告)日：2014-12-11

申请号：US14165354

申请日：2014-01-27

Applicant: VIA TECHNOLOGIES, INC.

Inventor： Rodney E. Hooker ,  Terry Parks ,  John Michael Greer

IPC: G06F9/30

CPC classification number: G06F9/30058 ,  G06F9/3848 ,  G06F9/3851

Abstract: A microprocessor includes a predicting unit and a control unit. The control unit controls the predicting unit to accumulate a history of characteristics of executed instructions and makes predictions related to subsequent instructions based on the history while the microprocessor is running a first thread. The control unit also detects a transition from running the first thread to running a second thread and controls the predicting unit to selectively suspend accumulating the history and making the predictions using the history while running the second thread. The predicting unit makes static predictions while running the second thread. The selectivity may be based on the privilege level, identity or length of the second thread, static prediction effectiveness during a previous execution instance of the thread, whether the transition was made due to a system call, and whether the second thread is an interrupt handler.

Abstract translation: 微处理器包括预测单元和控制单元。 控制单元控制预测单元累积执行指令的特征历史，并且在微处理器运行第一线程的同时基于历史来进行与后续指令相关的预测。 控制单元还检测从运行第一线程到运行第二线程的转变，并且控制预测单元选择性地暂停累积历史并且在运行第二线程时使用历史进行预测。 预测单元在运行第二个线程时进行静态预测。 选择性可以基于第二线程的特权级别，身份或长度，线程的先前执行实例期间的静态预测有效性，是否由于系统调用而进行转换，以及第二线程是否是中断处理程序 。

公开(公告)号：US08850229B2

公开(公告)日：2014-09-30

申请号：US14066270

申请日：2013-10-29

Applicant: VIA Technologies, Inc.

Inventor： G. Glenn Henry ,  Terry Parks ,  Brent Bean ,  Thomas A. Crispin

IPC: G06F21/00 ,  G06F21/71 ,  G06F9/30 ,  H04L9/08 ,  G06F21/52 ,  G06F21/60 ,  G06F12/08 ,  G06F21/54 ,  H04L9/06 ,  G06F21/72

CPC classification number: H04L9/0827 ,  G06F9/30003 ,  G06F9/30079 ,  G06F9/30178 ,  G06F9/30189 ,  G06F12/0875 ,  G06F21/52 ,  G06F21/54 ,  G06F21/602 ,  G06F21/71 ,  G06F21/72 ,  G06F2212/402 ,  G06F2212/452 ,  G06F2221/2107 ,  H04L9/0618 ,  H04L9/0861 ,  H04L9/0891 ,  H04L9/0894 ,  H04L2209/12 ,  H04L2209/20

Abstract: An apparatus for generating a decryption key for use to decrypt a block of encrypted instruction data being fetched from an instruction cache in a microprocessor at a fetch address includes a first multiplexer that selects a first key value from a plurality of key values based on a first portion of the fetch address. A second multiplexer selects a second key value from the plurality of key values based on the first portion of the fetch address. A rotater rotates the first key value based on a second portion of the fetch address. An arithmetic unit selectively adds or subtracts the rotated first key value to or from the second key value based on a third portion of the fetch address to generate the decryption key.

Abstract translation: 一种用于产生解密密钥的装置，用于解密从提取地址的微处理器中的指令高速缓存取出的加密指令数据块，其包括：第一多路复用器，其基于第一和第二多个键值从多个键值中选择第一键值 提取地址的一部分。 第二多路复用器根据提取地址的第一部分从多个键值中选择第二键值。 旋转器基于获取地址的第二部分旋转第一键值。 算术单元基于获取地址的第三部分，有选择地向第二密钥值添加或减去所转动的第一密钥值，以生成解密密钥。