公开(公告)号：US07157367B2

公开(公告)日：2007-01-02

申请号：US10861149

申请日：2004-06-04

申请人： Hway Chi Lin ,  Yi-Lung Cheng ,  Chao-Hsiung Wang

发明人： Hway Chi Lin ,  Yi-Lung Cheng ,  Chao-Hsiung Wang

IPC分类号： H01L21/4763

CPC分类号： H01L21/76802 ,  H01L2924/0002 ,  H01L2924/00

摘要： A substrate is provided having semiconductor device structures formed in and on the substrate. The semiconductor device structures comprise conductor layers embedded in openings in dielectric layers having a dielectric constant of less than 4.5. The dielectric layer has a roughness between the dielectric and the conductor wherein the roughness of the dielectric layer divided by the thickness of a barrier layer underlying the conductor layer is 0 to 1. The integrated circuit structure is prepared for failure analysis by removing the low dielectric constant dielectric layers and exposing the conductor layers for further failure analysis by optical examination or scanning electron microscope (SEM).

摘要翻译： 提供了一种衬底，其具有形成在衬底中和衬底上的半导体器件结构。 半导体器件结构包括嵌入介电常数小于4.5的电介质层的开口中的导体层。 电介质层在电介质和导体之间具有粗糙度，其中介电层的粗糙度除以导体层下面的阻挡层的厚度为0-1。集成电路结构通过去除低电介质来制备用于故障分析 恒电介质层，并通过光学检查或扫描电子显微镜（SEM）暴露导体层进行进一步的故障分析。

公开(公告)号：US20050077627A1

公开(公告)日：2005-04-14

申请号：US10684224

申请日：2003-10-10

申请人： Chen-Hua Yu ,  Horng-Huei Tseng ,  Chenming Hu ,  Chao-Hsiung Wang

发明人： Chen-Hua Yu ,  Horng-Huei Tseng ,  Chenming Hu ,  Chao-Hsiung Wang

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L21/4763 ,  H01L23/48

CPC分类号： H01L21/76846 ,  H01L21/76849 ,  H01L21/7685 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor devices and methods of forming the semiconductor devices using an HTS (High Temperature Superconductor) layer in combination with a typical diffusion layer between the dielectric material and the copper (or other metal) conductive wiring. The HTS layer includes a superconductor material comprised of barium copper oxide and a rare earth element. The rare earth element yttrium is particularly suitable. For semiconductor devices having other semiconductor circuits or elements above the wiring, a capping layer of HTS material is deposited over the wiring before a cover layer of dielectric is deposited.

摘要翻译： 使用HTS（高温超导体）层与介电材料和铜（或其它金属）导电布线之间的典型扩散层组合形成半导体器件的半导体器件和方法。 HTS层包括由氧化钡钡和稀土元素构成的超导体材料。 稀土元素钇特别适合。 对于具有其它半导体电路或布线之上的元件的半导体器件，在沉积覆盖层的电介质之前，在布线上沉积HTS材料的覆盖层。

公开(公告)号：US09893163B2

公开(公告)日：2018-02-13

申请号：US13289038

申请日：2011-11-04

申请人： Chi-Wen Liu ,  Chao-Hsiung Wang

发明人： Chi-Wen Liu ,  Chao-Hsiung Wang

IPC分类号： H01L29/94 ,  H01L29/66 ,  H01L49/02

CPC分类号： H01L29/66181 ,  H01L28/92 ,  H01L29/94 ,  H01L29/945

摘要： A 3D capacitor and method for fabricating a 3D capacitor is disclosed. An exemplary 3D capacitor includes a substrate including a fin structure, the fin structure including a plurality of fins. The 3D capacitor further includes an insulation material disposed on the substrate and between each of the plurality of fins. The 3D capacitor further includes a dielectric layer disposed on each of the plurality of fins. The 3D capacitor further includes a first electrode disposed on a first portion of the fin structure. The first electrode being in direct contact with a surface of the fin structure. The 3D capacitor further includes a second electrode disposed on a second portion of the fin structure. The second electrode being disposed directly on the dielectric layer and the first and second portions of the fin structure being different.

公开(公告)号：US09673280B2

公开(公告)日：2017-06-06

申请号：US11714416

申请日：2007-03-06

申请人： Chien-Chao Huang ,  Yee-Chia Yeo ,  Chao-Hsiung Wang ,  Chun-Chieh Lin ,  Chenming Hu

发明人： Chien-Chao Huang ,  Yee-Chia Yeo ,  Chao-Hsiung Wang ,  Chun-Chieh Lin ,  Chenming Hu

IPC分类号： H01L29/10 ,  H01L21/265 ,  H01L21/28 ,  H01L21/285 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02

CPC分类号： H01L29/1054 ,  H01L21/02142 ,  H01L21/265 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66636 ,  H01L29/7834

摘要： A method comprises providing a semiconductor alloy layer on a semiconductor substrate, forming a gate structure on the semiconductor alloy layer, forming source and drain regions in the semiconductor substrate on both sides of the gate structure, removing at least a portion of the semiconductor alloy layer overlying the source and drain regions, and forming a metal silicide region over the source and drain regions.

公开(公告)号：USRE45180E1

公开(公告)日：2014-10-07

申请号：US12792373

申请日：2010-06-02

申请人： Hung-Wei Chen ,  Tang-Xuan Zhong ,  Sheng-Da Liu ,  Chang-Yun Chang ,  Ping-Kun Wu ,  Chao-Hsiung Wang ,  Fu-Liang Yang

发明人： Hung-Wei Chen ,  Tang-Xuan Zhong ,  Sheng-Da Liu ,  Chang-Yun Chang ,  Ping-Kun Wu ,  Chao-Hsiung Wang ,  Fu-Liang Yang

IPC分类号： H01L21/311 ,  H01L21/00 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/336 ,  H01L27/085 ,  H01L29/06 ,  H01L29/04

CPC分类号： H01L21/823437 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823456 ,  H01L29/66795 ,  H01L29/7851

摘要： A method for forming a semiconductor device and a device made using the method are provided. In one example, the method includes forming a hard mask layer on a semiconductor substrate and patterning the hard mask layer to form multiple openings. The substrate is etched through the openings to form forming a plurality of trenches separating multiple semiconductor mesas. The trenches are partially filled with a dielectric material. The hard mask layer is removed and multiple-gate features are formed, with each multiple-gate feature being in contact with a top surface and sidewalls of at least one of the semiconductor mesas.

摘要翻译： 提供了一种用于形成半导体器件的方法和使用该方法制造的器件。 在一个示例中，该方法包括在半导体衬底上形成硬掩模层并且图案化硬掩模层以形成多个开口。 通过开口蚀刻衬底以形成分离多个半导体台面的多个沟槽。 沟槽部分地填充有电介质材料。 去除硬掩模层并形成多栅极特征，其中每个多栅极特征与至少一个半导体台面的顶表面和侧壁接触。

公开(公告)号：USRE45165E1

公开(公告)日：2014-09-30

申请号：US13372622

申请日：2012-02-14

申请人： Hung-Wei Chen ,  Tang-Xuan Zhong ,  Sheng-Da Liu ,  Chang-Yu Chang ,  Ping-Kun Wu ,  Chao-Hsiung Wang ,  Fu-Liang Yang

发明人： Hung-Wei Chen ,  Tang-Xuan Zhong ,  Sheng-Da Liu ,  Chang-Yu Chang ,  Ping-Kun Wu ,  Chao-Hsiung Wang ,  Fu-Liang Yang

IPC分类号： H01L23/12 ,  H01L23/053 ,  H01L29/06 ,  H01L27/085 ,  H01L29/04

CPC分类号： H01L29/1079 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823456 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/7851 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a semiconductor device and a device made using the method are provided. In one example, the method includes forming a hard mask layer on a semiconductor substrate and patterning the hard mask layer to form multiple openings. The substrate is etched through the openings to form forming a plurality of trenches separating multiple semiconductor mesas. The trenches are partially filled with a dielectric material. The hard mask layer is removed and multiple-gate features are formed, with each multiple-gate feature being in contact with a top surface and sidewalls of at least one of the semiconductor mesas.

公开(公告)号：US20130113072A1

公开(公告)日：2013-05-09

申请号：US13289038

申请日：2011-11-04

申请人： Chi-Wen Liu ,  Chao-Hsiung Wang

发明人： Chi-Wen Liu ,  Chao-Hsiung Wang

IPC分类号： H01L29/92 ,  H01L21/02

CPC分类号： H01L29/66181 ,  H01L28/92 ,  H01L29/94 ,  H01L29/945

摘要： A 3D capacitor and method for fabricating a 3D capacitor is disclosed. An exemplary 3D capacitor includes a substrate including a fin structure, the fin structure including a plurality of fins. The 3D capacitor further includes an insulation material disposed on the substrate and between each of the plurality of fins. The 3D capacitor further includes a dielectric layer disposed on each of the plurality of fins. The 3D capacitor further includes a first electrode disposed on a first portion of the fin structure. The first electrode being in direct contact with a surface of the fin structure. The 3D capacitor further includes a second electrode disposed on a second portion of the fin structure. The second electrode being disposed directly on the dielectric layer and the first and second portions of the fin structure being different.

摘要翻译： 公开了用于制造3D电容器的3D电容器和方法。 示例性3D电容器包括包括鳍结构的衬底，鳍结构包括多个翅片。 3D电容器还包括设置在基板上并且在多个翅片中的每一个之间的绝缘材料。 3D电容器还包括设置在多个鳍片中的每一个上的电介质层。 3D电容器还包括设置在翅片结构的第一部分上的第一电极。 第一电极与翅片结构的表面直接接触。 3D电容器还包括设置在鳍结构的第二部分上的第二电极。 第二电极直接设置在电介质层上，翅片结构的第一和第二部分是不同的。

公开(公告)号：US20130082304A1

公开(公告)日：2013-04-04

申请号：US13252892

申请日：2011-10-04

申请人： Chi-Wen Liu ,  Chao-Hsiung Wang

发明人： Chi-Wen Liu ,  Chao-Hsiung Wang

IPC分类号： H01L29/772 ,  H01L21/336

CPC分类号： H01L27/0886 ,  H01L21/823821 ,  H01L29/0847 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

摘要： A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a fin structure disposed over the substrate. The fin structure includes one or more fins. The semiconductor device further includes an insulation material disposed on the substrate. The semiconductor device further includes a gate structure disposed on a portion of the fin structure and on a portion of the insulation material. The gate structure traverses each fin of the fin structure. The semiconductor device further includes a source and drain feature formed from a material having a continuous and uninterrupted surface area. The source and drain feature includes a surface in a plane that is in direct contact with a surface in a parallel plane of the insulation material, each of the one or more fins of the fin structure, and the gate structure.

摘要翻译： 公开了一种用于制造半导体器件的半导体器件和方法。 示例性半导体器件包括：衬底，其包括设置在衬底上的鳍结构。 翅片结构包括一个或多个翅片。 半导体器件还包括设置在基板上的绝缘材料。 半导体器件还包括设置在鳍结构的一部分上和绝缘材料的一部分上的栅极结构。 栅极结构横穿翅片结构的每个翅片。 半导体器件还包括由具有连续且不间断表面积的材料形成的源极和漏极特征。 源极和漏极特征包括在与绝缘材料的平行平面中的表面直接接触的平面中的表面，翅片结构的一个或多个翅片中的每一个以及栅极结构。

公开(公告)号：US08288842B2

公开(公告)日：2012-10-16

申请号：US11655008

申请日：2007-01-18

申请人： Hsin-Hui Lee ,  Chien-Chao Huang ,  Chao-Hsiung Wang ,  Fu-Liang Yang ,  Chenming Hu

发明人： Hsin-Hui Lee ,  Chien-Chao Huang ,  Chao-Hsiung Wang ,  Fu-Liang Yang ,  Chenming Hu

IPC分类号： H01L23/544 ,  H01L21/301

CPC分类号： H01L21/78 ,  B28D5/00

摘要： A method provides for dicing a wafer having a base material with a diamond structure. The wafer first undergoes a polishing process, in which a predetermined portion of the wafer is polished away from its back side. The wafer is then diced through at least one line along a direction at a predetermined offset angle from a natural cleavage direction of the diamond structure. A wafer is produced with one or more dies formed thereon with at least one of its edges at an offset angle from a natural cleavage direction of a diamond structure of a base material forming the wafer. At least one dicing line has one or more protection elements for protecting the dies from undesired cracking while the wafer is being diced along the dicing line.

摘要翻译： 一种方法提供用具有金刚石结构的具有基底材料的晶片切割。 晶片首先进行抛光处理，其中将晶片的预定部分从其背面抛光。 然后将晶片沿着与金刚石结构的天然裂解方向成预定偏移角的方向通过至少一条线切割。 制造具有一个或多个模具的晶片，其上的至少一个边缘与形成晶片的基底材料的金刚石结构的天然裂解方向成偏移角。 至少一个切割线具有一个或多个保护元件，用于在晶片沿着切割线切割时保护模具不受不期望的开裂。

公开(公告)号：US07381649B2

公开(公告)日：2008-06-03

申请号：US11192494

申请日：2005-07-29

申请人： Hung-Wei Chen ,  Tang-Xuan Zhong ,  Sheng-Da Liu ,  Chang-Yun Chang ,  Ping-Kun Wu ,  Chao-Hsiung Wang ,  Fu-Liang Yang

发明人： Hung-Wei Chen ,  Tang-Xuan Zhong ,  Sheng-Da Liu ,  Chang-Yun Chang ,  Ping-Kun Wu ,  Chao-Hsiung Wang ,  Fu-Liang Yang

IPC分类号： H01L21/00

CPC分类号： H01L21/823437 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823456 ,  H01L29/66795 ,  H01L29/7851

摘要： A method for forming a semiconductor device and a device made using the method are provided. In one example, the method includes forming a hard mask layer on a semiconductor substrate and patterning the hard mask layer to form multiple openings. The substrate is etched through the openings to form forming a plurality of trenches separating multiple semiconductor mesas. The trenches are partially filled with a dielectric material. The hard mask layer is removed and multiple-gate features are formed, with each multiple-gate feature being in contact with a top surface and sidewalls of at least one of the semiconductor mesas.

摘要翻译： 提供了一种用于形成半导体器件的方法和使用该方法制造的器件。 在一个示例中，该方法包括在半导体衬底上形成硬掩模层并且图案化硬掩模层以形成多个开口。 通过开口蚀刻衬底以形成分离多个半导体台面的多个沟槽。 沟槽部分地填充有电介质材料。 去除硬掩模层并形成多栅极特征，其中每个多栅极特征与至少一个半导体台面的顶表面和侧壁接触。