Abstract:
A system for mitigating power supply and power distribution system noise response by throttling execution units based upon voltage sensing in a circuit is provided. A sensing unit senses the voltage of a circuit. The sensing unit determines if the execution of another execution unit will cause the circuit voltage to drop below a threshold level. In response to a determination that the execution of another execution unit will cause the circuit voltage to drop below the threshold level, the execution unit is throttled.
Abstract:
An auto routing method and system provides optimized circuit routing while maintaining proper reference return paths for critical signals. Critical signal paths are auto-routed simultaneously with corresponding reference return paths, and the reference return paths can be merged into reference planes if they are adjacent to regions connected to the same reference net. The reference return paths may be in a plane adjacent to the signal path plane in the same channel, or the reference returns may be routed in adjacent channels in the same plane as the signal path. A check may be performed on endpoints of each critical signal path to determine whether a reference return via is present within a proximity tolerance of the signal path endpoints, and a reference return via placed if not.
Abstract:
A circuit and a method for detecting noise events in a system with time variable operating points is provided. A switched capacitor filter comprising a plurality of capacitor units, samples a first voltage to determine an average of a set of voltage measurements, forming an average voltage. A filter control unit controls the plurality of capacitor units in the switched capacitor filter. A comparing unit compares the average voltage to the first voltage to form a comparison. A signaling unit generates a signal to instruct circuits in a processor to initiate actions to keep the first voltage from drooping below a threshold level in response to the comparison.
Abstract:
A circuit for detecting noise events in a system with time variable operating points is provided. A first voltage, which is averaged over time, is compared to a second voltage. A signal is generated to instruct circuits within a processor to initiate actions to keep a voltage from drooping further.
Abstract:
A test card system for use in product development includes a device under test (DUT). The DUT comprises: a mount plane; a power input port coupled to the mount plane; a JTAG input port coupled to the mount plane; a clock signal distribution network coupled to the JTAG input port; a plurality of latches coupled to the clock signal distribution network and the power input port; and an output port coupled to the plurality of latches. A test card (TC) couples to the DUT, comprising: a JTAG interface coupled to the DUT JTAG input port and configured to provide test data to the DUT; a clock module coupled to the DUT clock signal distribution network and configured to generate a clock signal; and an analysis module coupled to the DUT output port and configured to receive data from the DUT.
Abstract:
A system and method of integrated circuit control for in situ impedance measurement including a system with a plurality of functional partitions in a clocked logic type integrated circuit, the functional partitions having a communication controller and a modulation gate, the modulation gate receiving a clock signal and a modulation signal and generating a modulated clock signal for the functional partition; at least one of the communication controllers receiving an in-band signal and selectively communicating the in-band signal to the other communication controllers; and at least one of the functional partitions having a modulator, the modulator receiving the clock signal and a modulation control signal and generating the modulation signal.
Abstract:
A system for minimizing the length of the longest diagonal interconnection. A multiple chip module may comprise a first chip connected to a second chip located diagonally to the first chip. The first and second chip are interconnected by one or more interconnections commonly referred to as diagonal interconnections. Since the one or more diagonal interconnections between the first chip and the second chip are interconnected between a set of pins on each chip that form a triangular pattern, the longest diagonal interconnection is substantially the same length as the length of the longest orthogonal interconnection. Furthermore, since the one or more diagonal interconnections between the first chip and the second chip are interconnected between a set of pins on each chip that form a triangular pattern, the longest diagonal interconnection is substantially the same length as the length of the second longest diagonal interconnection.
Abstract:
Mechanisms for interconnecting and distributing signals and power between PCBs are provided. A first PCB having land grid arrays (LGAs) and a first wiring layer designed for interconnect components on the first PCB, and a second wiring layer for connecting the components to a second PCB, are provided. The second PCB has opposed parallel first and second surfaces, the first surface having a LGA. A wiring layer designed to interconnect components on the second PCB, and a layer for interconnecting the components on the second PCB with the components on the first PCB, are provided. A first interposer couples to a LGA of a first surface of the first PCB and connects a component to the first PCB. A second interposer is sandwiched between and couples to a LGA of a second surface of the first PCB and to the LGA of the first surface of the second PCB.
Abstract:
A first selection of mesh line segments of a mesh layer are of a first width and a second selection of mesh line segments of the mesh layer are of a second width, wherein the second width is greater than the first width. The second selection of mesh line segments of the second width are positioned in parallel to a selection of signal lines in a signal layer that are likely to introduce crosstalk, wherein the widening of the mesh line segments shadowing the selection of signal lines increases the likelihood that the return current associated with the signal will flow in the wider mesh line segment, thereby increasing the likelihood of containing the electromagnetic fields associated with the signal such that crosstalk to other signals is reduced or contained.
Abstract:
A system, method, and motherboard assembly are described for interconnecting and distributing signals and power between co-planar boards that function as a single motherboard. The motherboard assembly includes a multilayered first printed circuit board having opposed parallel first and second surfaces, each having at least one land grid array (LGA) disposed thereon. The assembly further includes at least one wiring layer (Y) designed to only electrically interconnect components on or within the first PCB, and at least one wiring layer (X) designed to only electrically connect the components on the first PCB to a multilayered second PCB. The multilayered second PCB has opposed parallel first and second surfaces, the first surface having at least one LGA disposed thereon. It further includes at least one wiring layer (V) designed to only electrically interconnect components on or within the second PCB, and at least one layer (X) designed to only electrically interconnect the components on the second PCB with the components on the first PCB. A first LGA interposer couples to the LGA disposed on the first surface of the first PCB, and electrically connects at least one component to the first PCB. A second LGA interposer is sandwiched between and couples to the LGA disposed on the second surface of the first PCB and to the LGA disposed on the first surface of the second PCB. It electrically connects the first PCB to components on the second PCB.