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161 条记录 (耗时 0.037 秒)

    Particle sensor
    31.
    发明授权
    Particle sensor 失效

    公开(公告)号：US06611611B2

    公开(公告)日：2003-08-26

    申请号：US09926635

    申请日：2001-11-28

    申请人： Shoichi Oka ,  Masanori Hayashi ,  Shinji Kirihata ,  Takayuki Nishikawa ,  Koji Sakamoto ,  Takeshi Wada

    发明人： Shoichi Oka ,  Masanori Hayashi ,  Shinji Kirihata ,  Takayuki Nishikawa ,  Koji Sakamoto ,  Takeshi Wada

    IPC分类号： G06K900

    CPC分类号： G01N21/53 ,  G01N2201/127 ,  H03G1/0088

    摘要： A particle sensor has a gain control and an offset voltage adjustment so as to provide a consistent sensor output indicative of the particle density in match with a predetermined relationship between the sensor output and the particle density, while compensating for background noises. The gain control and the offset voltage adjustment are realized respectively by digitally controllable variable resistor networks each having a plurality of switches. A memory module is included in the sensor to store instruction data for control of the switches and therefore responsible for the gain control and the offset voltage adjustment. In particular, the particle sensor includes a memory interface which enables the selective use of two types of memory means, one is an intelligent memory module composed of EEPROM and a microcomputer, and the other is a normal memory module consisting of EEPROM.

    Nonvolatile semiconductor memory device
    34.
    发明授权
    Nonvolatile semiconductor memory device 失效
    非易失性半导体存储器件

    公开(公告)号：US6157576A

    公开(公告)日：2000-12-05

    申请号：US393301

    申请日：1999-09-10

    申请人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

    发明人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

    IPC分类号： G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C16/32 ,  G11C16/34 ,  G11C16/04

    CPC分类号： G11C16/3445 ,  G11C16/06 ,  G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C16/32 ,  G11C16/344 ,  G11C2216/20

    摘要： Within an EEPROM having a memory array in which the electrically erasable nonvolatile storage elements are arranged in a matrix form, an erasing control circuit is included, which performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith in accordance with externally supplied erasing operation instructions. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation. In one aspect of the present invention, a Vcc power source is applied to a source region or a drain region of each nonvolatile semiconductor memory cell, and an erasure voltage having a polarity opposite to that of the Vcc power source is applied to a control gate electrode. The erasure voltage is supplied to a voltage conversion circuit provided within the nonvolatile memory device. Accordingly, erasure operation can be realized by the Vcc single power source. Further, substantial terminals of the collective erasure operation are individually controlled for every memory element or every collective memory element in response to the individual erasure speed of each memory element.

    摘要翻译： 在具有其中电可擦除非易失性存储元件以矩阵形式布置的存储器阵列的EEPROM中，包括擦除控制电路，其在执行擦除操作之后在对应的存储器单元上至少执行一次读出操作 根据外部提供的擦除操作指令。 擦除操作由内部擦除控制电路自动执行，同时响应于来自微处理器的指令，EEPROM与微处理器电隔离。 微处理器的控制只需要稍微短的时间段，在擦除操作期间EEPROM保留在系统中时，指令擦除开始。 在本发明的一个方面中，将Vcc电源施加到每个非易失性半导体存储单元的源极区域或漏极区域，并且将具有与Vcc电源的极性相反的极性的擦除电压施加到控制栅极 电极。 擦除电压被提供给设置在非易失性存储器件内的电压转换电路。 因此，可以通过Vcc单电源实现擦除操作。 此外，响应于每个存储元件的单独擦除速度，对于每个存储元件或每个集合存储元件单独控制集体擦除操作的实质端子。

    Nonvolatile semiconductor memory device
    35.
    发明授权
    Nonvolatile semiconductor memory device 失效

    公开(公告)号：US5781476A

    公开(公告)日：1998-07-14

    申请号：US456797

    申请日：1995-06-01

    申请人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

    发明人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

    IPC分类号： G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C16/32 ,  G11C16/34 ,  G11C11/34

    CPC分类号： G11C16/3445 ,  G11C16/06 ,  G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C16/32 ,  G11C16/344 ,  G11C2216/20

    摘要： Within an EEPROM having a memory array in which the electrically erasable nonvolatile storage elements are arranged in a matrix form, an erasing control circuit is included, which performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith in accordance with externally supplied erasing operation instructions. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation. In one aspect of the present invention, a Vcc power source is applied to a source region or a drain region of each nonvolatile semiconductor memory cell, and an erasure voltage having a polarity opposite to that of the Vcc power source is applied to a control gate electrode. The erasure voltage is supplied to a voltage conversion circuit provided within the nonvolatile memory device. Accordingly, erasure operation can be realized by the Vcc single power source. Further, substantial terminals of the collective erasure operation are individually controlled for every memory element or every collective memory element in response to the individual erasure speed of each memory element.

    Process and apparatus, for electron beam welding of a member partially enclosed in vacuum chamber, and the member formed thereby
    39.
    发明授权
    Process and apparatus, for electron beam welding of a member partially enclosed in vacuum chamber, and the member formed thereby 失效
    用于部分包围在真空室中的部件的电子束焊接的工艺和装置以及由此形成的部件

    公开(公告)号：US5170028A

    公开(公告)日：1992-12-08

    申请号：US564581

    申请日：1990-08-09

    申请人： Takeshi Wada ,  Tatsuo Yonezawa ,  Noboru Umehara ,  Toshio Nemoto ,  Toshio Namatame

    发明人： Takeshi Wada ,  Tatsuo Yonezawa ,  Noboru Umehara ,  Toshio Nemoto ,  Toshio Namatame

    IPC分类号： B23K15/06 ,  H01J37/18

    CPC分类号： H01J37/18 ,  B23K15/06 ,  H01J2237/2005 ,  H01J2237/3104

    摘要： An apparatus for welding of a member to be welded in a vacuum chamber accommodating a part of the member, comprises a housing for defining the vacuum chamber, the housing including upper and lower housings between which the member to be welded is held, the upper and lower housings each having front and rear sides; an electron gun mounted on the upper housing; a drive device for moving the electron gun in a welding direction; an adjustment member or adjustment liner plate disposed on the lower housing for defining spaces allowing a part of the member to be welded to fit in at the front and rear sides of the lower housing so that the entirety of a welding portion of the member is in the vacuum chamber and both sides of the welding line are exposed in vacuum; sealing material for sealing between the housing, the adjustment member or adjustment liner plate and the member to be welded.

    摘要翻译： 一种用于将待焊接的部件焊接在容纳部件的一部分的真空室中的装置，包括用于限定真空室的壳体，所述壳体包括上部和下部壳体，所述待焊接部件保持在其之间， 下壳体各自具有前侧和后侧; 安装在上壳体上的电子枪; 用于沿焊接方向移动电子枪的驱动装置; 设置在下壳体上的调节构件或调节衬板，用于限定允许部件的一部分被焊接以配合在下壳体的前侧和后侧的空间，使得构件的焊接部分的整体处于 真空室和焊接线的两侧在真空中暴露; 密封材料用于在壳体，调节构件或调节衬板与待焊接构件之间进行密封。

    Low temperature sintered ceramic capacitor with a temperature compensating capability, and method of manufacture
    40.
    发明授权
    Low temperature sintered ceramic capacitor with a temperature compensating capability, and method of manufacture 失效
    具有温度补偿能力的低温烧结陶瓷电容器及其制造方法

    公开(公告)号：US4700266A

    公开(公告)日：1987-10-13

    申请号：US945075

    申请日：1986-12-22

    申请人： Hirokazu Chazono ,  Hiroshi Kishi ,  Shunji Murai ,  Masami Fukui ,  Takeshi Wada

    发明人： Hirokazu Chazono ,  Hiroshi Kishi ,  Shunji Murai ,  Masami Fukui ,  Takeshi Wada

    IPC分类号： H01G4/30 ,  C04B35/47 ,  C04B35/49 ,  H01B3/12 ,  H01G4/12 ,  C04B35/46

    CPC分类号： H01G4/1245 ,  C04B35/47 ,  C04B35/49

    摘要： A temperature compensating capacitor of monolithic or multilayered configuration comprising a dielectric ceramic body and at least two electrodes buried therein. The ceramic body is composed of a major ingredient expressed by the formula, {(Sr.sub.1-x Ca.sub.x)O}.sub.k (Ti.sub.1-y Zr.sub.y)O.sub.2, where x, k and y are numerals in the ranges of 0.005 to 0.995 inclusive, 1.00 to 1.04 inclusive, and 0.005 to 0.100 inclusive, respectively. To this major ingredient is added a minor proportion of a mixture of lithium oxide, silicon dioxide, and one or more metal oxides selected from among barium oxide, magnesium oxide, zinc oxide, strontium oxide and calcium oxide. For the fabrication of capacitors the mixture of the above major ingredient and additives in finely divided form are formed into moldings of desired shape and size, each with at least two electrodes buried therein. The moldings and electrodes are cosintered in a reductive or neutral atmosphere and then are reheated at a lower temperature in an oxidative atmosphere. the cosintering temperature can be so low that nickel or like base metal can be employed as the electrode material.

    摘要翻译： 一种单片或多层结构的温度补偿电容器，包括介电陶瓷体和埋在其中的至少两个电极。 陶瓷体由式（{（Sr1-xCax）O} k（Ti1-yZry）O2）表示的主要成分组成，其中x，k和y为0.005〜0.995的数值，1.00〜1.04 分别为0.005〜0.100。 在该主要成分中加入少量的氧化锂，二氧化硅和选自氧化钡，氧化镁，氧化锌，氧化锶和氧化钙中的一种或多种金属氧化物的混合物。 为了制造电容器，将上述主要成分和细分散形式的添加剂的混合物形成为所需形状和尺寸的模制品，其中至少埋设有两个电极。 模制品和电极在还原或中性气氛中共烧结，然后在较低温度下在氧化气氛中再加热。 整个烧结温度可以低到可以使用镍或类似的贱金属作为电极材料。