公开(公告)号：US09318502B2

公开(公告)日：2016-04-19

申请号：US14678526

申请日：2015-04-03

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jai-Ick Son ,  Sunghoon Kim

IPC分类号： H01L27/115 ,  H01L23/535 ,  H01L23/528 ,  H01L27/12

CPC分类号： H01L27/11573 ,  H01L27/11514 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/1203

摘要： A nonvolatile memory device includes a memory cell array and a peripheral circuit. The peripheral circuit is connected to the memory cell array through conductive lines and includes transistors. Each of the transistors is formed on the substrate and includes first and second regions and a gate electrode. In at least one of the transistors, the first region is connected to at least one of the conductive lines through first contact plugs extending in the direction perpendicular to the substrate, and second contact plugs extending in the direction perpendicular to the substrate. A contact area of each of the first contact plugs is different from a contact area of each of the second contact plugs.

摘要翻译： 非易失性存储器件包括存储单元阵列和外围电路。 外围电路通过导线连接到存储单元阵列，并包括晶体管。 每个晶体管形成在衬底上并且包括第一和第二区域以及栅电极。 在至少一个晶体管中，第一区域通过沿垂直于衬底的方向延伸的第一接触插塞连接到至少一个导电线，第二接触插塞沿垂直于衬底的方向延伸。 每个第一接触插塞的接触区域与每个第二接触插塞的接触面积不同。

公开(公告)号：US09012292B2

公开(公告)日：2015-04-21

申请号：US13175652

申请日：2011-07-01

申请人： Sang-Yun Lee

发明人： Sang-Yun Lee

IPC分类号： H01L21/20 ,  H01L49/02 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L21/84 ,  H01L27/06 ,  H01L27/12

CPC分类号： H01L28/91 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/10808 ,  H01L27/1082 ,  H01L27/10852 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11514 ,  H01L27/1207

摘要： A method for fabricating semiconductor memory device, includes providing a semiconductor substrate; forming a lower region which includes a first data storage device, which is carried by the semiconductor substrate; forming a switching device which is carried by the first data storage device; and forming an upper region which includes a second data storage device, which is carried by the switching device. The step of forming the first storage device includes forming a first electrode having a cylindrical or pillar shape, the first electrode being connected to the switching device.

摘要翻译： 一种制造半导体存储器件的方法，包括提供半导体衬底; 形成下部区域，其包括由所述半导体基板承载的第一数据存储装置; 形成由所述第一数据存储装置承载的切换装置; 以及形成由所述切换装置携带的包括第二数据存储装置的上部区域。 形成第一存储装置的步骤包括形成具有圆柱形或柱状的第一电极，第一电极连接到开关装置。

公开(公告)号：US08878156B2

公开(公告)日：2014-11-04

申请号：US13680037

申请日：2012-11-17

申请人： Avalanche Technology Inc.

发明人： Kimihiro Satoh ,  Yiming Huai

IPC分类号： H01L29/04 ,  H01L29/78 ,  H01L45/00 ,  H01L27/115

CPC分类号： H01L45/1233 ,  H01L27/11507 ,  H01L27/11514 ,  H01L27/228 ,  H01L27/2436 ,  H01L27/2454 ,  H01L27/2463 ,  H01L27/2481 ,  H01L29/7827 ,  H01L43/02 ,  H01L43/08 ,  H01L45/04 ,  H01L45/06 ,  H01L45/08 ,  H01L45/085 ,  H01L45/144 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147

摘要： A memory device comprises a semiconductor substrate having a plurality of parallel trenches therein, a memory region formed in the substrate including an array of memory cells having a plurality of vertical selection transistors with respective channels formed in trench sidewalls, a plurality of buried source electrodes in trench bottoms, a plurality of paired gate electrodes formed on paired trench sidewalls, a first and second stitch region disposed adjacent the memory region along a trench direction including a first and second row of gate contacts, respectively, and a row of source contacts disposed in the first or second stitch region with each of the source contacts coupled to a respective one of the source electrodes. One of each pair of the gate electrodes is coupled to a respective one of the first row of gate contacts and the other one of each pair of gate electrodes is coupled to a respective one of the second row of gate contacts.

摘要翻译： 存储器件包括其中具有多个平行沟槽的半导体衬底，形成在衬底中的存储区包括存储单元阵列，存储单元阵列具有形成在沟槽侧壁中的各个沟道的多个垂直选择晶体管，多个埋入源电​​极 沟槽底部，形成在一对沟槽侧壁上的多个成对栅极电极，分别沿着包括第一和第二排栅极触点的沟槽方向邻近存储区域设置的第一和第二缝合区域，以及一排源极触点， 第一或第二针脚区域，其中每个源极触点耦合到相应的一个源极电极。 每对栅电极中的一个耦合到第一行栅极触点中的相应一个，并且每对栅电极中的另一个耦合到第二行栅极触点的相应一个。

公开(公告)号：US20140138600A1

公开(公告)日：2014-05-22

申请号：US13680037

申请日：2012-11-17

申请人： Kimihiro SATOH ,  Yiming Huai

发明人： Kimihiro SATOH ,  Yiming Huai

IPC分类号： H01L45/00 ,  H01L27/088

CPC分类号： H01L45/1233 ,  H01L27/11507 ,  H01L27/11514 ,  H01L27/228 ,  H01L27/2436 ,  H01L27/2454 ,  H01L27/2463 ,  H01L27/2481 ,  H01L29/7827 ,  H01L43/02 ,  H01L43/08 ,  H01L45/04 ,  H01L45/06 ,  H01L45/08 ,  H01L45/085 ,  H01L45/144 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147

摘要： A memory device comprises a semiconductor substrate having a plurality of parallel trenches therein, a memory region formed in the substrate including an array of memory cells having a plurality of vertical selection transistors with respective channels formed in trench sidewalls, a plurality of buried source electrodes in trench bottoms, a plurality of paired gate electrodes formed on paired trench sidewalls, a first and second stitch region disposed adjacent the memory region along a trench direction including a first and second row of gate contacts, respectively, and a row of source contacts disposed in the first or second stitch region with each of the source contacts coupled to a respective one of the source electrodes. One of each pair of the gate electrodes is coupled to a respective one of the first row of gate contacts and the other one of each pair of gate electrodes is coupled to a respective one of the second row of gate contacts.

摘要翻译： 存储器件包括其中具有多个平行沟槽的半导体衬底，形成在衬底中的存储区包括存储单元阵列，存储单元阵列具有形成在沟槽侧壁中的各个沟道的多个垂直选择晶体管，多个埋入源电​​极 沟槽底部，形成在一对沟槽侧壁上的多个成对栅极电极，分别沿着包括第一和第二排栅极触点的沟槽方向邻近存储区域设置的第一和第二缝合区域，以及一排源极触点， 第一或第二针脚区域，其中每个源极触点耦合到相应的一个源极电极。 每对栅电极中的一个耦合到第一行栅极触点中的相应一个，并且每对栅电极中的另一个耦合到第二行栅极触点的相应一个。

公开(公告)号：US08471263B2

公开(公告)日：2013-06-25

申请号：US12581722

申请日：2009-10-19

申请人： Sang-Yun Lee

发明人： Sang-Yun Lee

IPC分类号： H01L29/06

CPC分类号： H01L21/2007 ,  H01L27/0688 ,  H01L27/11514 ,  H01L27/228 ,  H01L27/2454

摘要： An information storage system includes a bonded semiconductor structure having a memory circuit region carried by an interconnect region. The memory circuit region includes a memory control device region having a vertically oriented memory control device. The memory circuit region includes a memory device region in communication with the memory control device region. The memory device region includes a memory device whose operation is controlled by the vertically oriented memory control device.

摘要翻译： 信息存储系统包括具有由互连区域承载的存储电路区域的键合半导体结构。 存储器电路区域包括具有垂直定向的存储器控​​制装置的存储器控​​制装置区域。 存储器电路区域包括与存储器控制装置区域通信的存储器件区域。 存储器件区域包括其操作由垂直定向的存储器控​​制器件控制的存储器件。

公开(公告)号：US20120254680A1

公开(公告)日：2012-10-04

申请号：US13431426

申请日：2012-03-27

申请人： Eun Chu Oh ,  KyoungLae Cho ,  Mankeun Seo ,  Junjin Kong

发明人： Eun Chu Oh ,  KyoungLae Cho ,  Mankeun Seo ,  Junjin Kong

IPC分类号： G11C29/08 ,  G06F11/26

CPC分类号： G06F11/1068 ,  G06F11/1016 ,  G06F11/1044 ,  G06F11/1048 ,  G06F11/1072 ,  G11C5/02 ,  G11C5/025 ,  G11C29/70 ,  G11C29/82 ,  G11C29/883 ,  H01L27/0688 ,  H01L27/11514 ,  H01L27/11521 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/281

摘要： Example embodiments relate to a bad area managing method of a nonvolatile memory device. The nonvolatile memory device may include a plurality of memory blocks and each block may contain memory layers stacked on a substrate. According to example embodiments, a method includes accessing one of the memory blocks, judging whether the accessed memory block includes at least one memory layer containing a bad memory cell. If a bad memory cell is detected, the method may further include configuring the memory device to treat the at least one memory layer of the accessed memory block as a bad area.

摘要翻译： 示例性实施例涉及非易失性存储器件的不良区域管理方法。 非易失性存储器件可以包括多个存储器块，并且每个块可以包含堆叠在衬底上的存储器层。 根据示例实施例，一种方法包括访问存储器块之一，判断所访问的存储器块是否包括至少一个包含坏存储器单元的存储器层。 如果检测到不良存储器单元，则该方法还可以包括配置存储器件以将所访问的存储器块的至少一个存储器层视为不良区域。

公开(公告)号：US20100213458A1

公开(公告)日：2010-08-26

申请号：US12390703

申请日：2009-02-23

申请人： Kirk D. Prall

发明人： Kirk D. Prall

IPC分类号： H01L29/12 ,  H01L21/34

CPC分类号： H01L27/12 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/8221 ,  H01L27/10873 ,  H01L27/11514 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11578 ,  H01L27/11597 ,  H01L27/1225 ,  H01L29/66825 ,  H01L29/7869 ,  H01L29/7881

摘要： Rigid semiconductor memory using amorphous metal oxide semiconductor channels are useful in the production of thin-film transistor memory devices. Such devices include single-layer and multi-layer memory arrays of volatile or non-volatile memory cells. The memory cells can be formed to have a gate stack overlying an amorphous metal oxide semiconductor, with amorphous metal oxide semiconductor channels.

摘要翻译： 使用非晶金属氧化物半导体通道的刚性半导体存储器可用于制造薄膜晶体管存储器件。 这样的设备包括易失性或非易失性存储单元的单层和多层存储器阵列。 存储单元可以形成为具有覆盖在非晶金属氧化物半导体上的栅极堆叠，具有无定形金属氧化物半导体沟道。

公开(公告)号：US20240008287A1

公开(公告)日：2024-01-04

申请号：US17857047

申请日：2022-07-04

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Po-Ting Lin ,  Wei-Chih Wen ,  Kai-Wen Cheng ,  Wu-Wei Tsai ,  Yu-Ming Hsiang ,  Yan-Yi Chen ,  Hai-Ching Chen ,  Yu-Ming Lin ,  Chung-Te Lin

IPC分类号： H01L27/11514 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L23/522 ,  H01L23/528

CPC分类号： H01L27/11514 ,  H01L29/516 ,  H01L29/6684 ,  H01L29/78391 ,  H01L23/5226 ,  H01L23/5283

摘要： A memory device and a manufacturing method thereof is described. The memory device includes a transistor structure over a substrate and a ferroelectric capacitor structure electrically connected with the transistor structure. The ferroelectric capacitor structure includes a top electrode layer, a bottom electrode layer and a ferroelectric stack sandwiched there-between. The ferroelectric stack includes a first ferroelectric layer, a first stabilizing layer, and one of a second ferroelectric layer or a second stabilizing layer. Materials of the first stabilizing layer and a second stabilizing layer include a metal oxide material.

公开(公告)号：US20240008285A1

公开(公告)日：2024-01-04

申请号：US17856877

申请日：2022-07-01

申请人： Intel Corporation

发明人： Abhishek Anil Sharma ,  Anand Murthy ,  Wilfred Gomes ,  Tahir Ghani

IPC分类号： H01L27/11514 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06

CPC分类号： H01L27/11514 ,  H01L29/0673 ,  H01L29/6684 ,  H01L29/78391

摘要： Bits are stored in an array with multiple capacitors sharing a single access transistor and a common plate coupled to the transistor. A single common select transistor accesses information stored in an array of capacitors, above and below the transistor and sharing a common plate. The common plate may be vertical and encircled by each of the other plates. The capacitors may be ferroelectric capacitors. In an integrated circuit system, the array may be coupled to a power supply and a cooling structure.

公开(公告)号：US11653505B2

公开(公告)日：2023-05-16

申请号：US17174027

申请日：2021-02-11

申请人： Micron Technology, Inc.

发明人： Hernan A. Castro ,  Stephen H. Tang ,  Stephen W. Russell

IPC分类号： H01L27/24 ,  H01L27/11514 ,  H01L45/00 ,  H01L23/522 ,  H01L21/768

CPC分类号： H01L27/249 ,  H01L27/11514 ,  H01L21/76816 ,  H01L23/5226 ,  H01L45/065 ,  H01L45/085 ,  H01L45/16 ,  H01L45/1683

摘要： Methods and apparatuses for a cross-point memory array and related fabrication techniques are described. The fabrication techniques described herein may facilitate concurrently building two or more decks of memory cells disposed in a cross-point architecture. Each deck of memory cells may include a plurality of first access lines (e.g., word lines), a plurality of second access lines (e.g., bit lines), and a memory component at each topological intersection of a first access line and a second access line. The fabrication technique may use a pattern of vias formed at a top layer of a composite stack, which may facilitate building a 3D memory array within the composite stack while using a reduced number of processing steps. The fabrication techniques may also be suitable for forming a socket region where the 3D memory array may be coupled with other components of a memory device.