公开(公告)号：US20170141101A1

公开(公告)日：2017-05-18

申请号：US15368958

申请日：2016-12-05

申请人： Texas Instruments Incorporated

发明人： Weidong Tian ,  YuGuo Wang ,  Tathagata Chatterjee ,  Rajni J. Aggarwal

IPC分类号： H01L27/06 ,  H01L29/06 ,  H01L21/8249 ,  H01L29/45 ,  H01L29/417 ,  H01L29/739 ,  H01L29/10

CPC分类号： H01L27/0623 ,  H01L21/8249 ,  H01L27/092 ,  H01L29/0688 ,  H01L29/1004 ,  H01L29/41708 ,  H01L29/423 ,  H01L29/456 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/7395

摘要： An integrated circuit includes an NMOS transistor, a PMOS transistor and a vertical bipolar transistor. The vertical bipolar transistor has an intrinsic base with a band barrier at least 25 meV high at a surface boundary of the intrinsic base, except at an emitter-base junction with an emitter, and except at a base-collector junction with a collector. The intrinsic base may be laterally surrounded by an extrinsic base with a higher dopant density than the intrinsic base, wherein a higher dopant density provides the band barrier at lateral surfaces of the intrinsic base. A gate may be disposed on a gate dielectric layer over a top surface boundary of the intrinsic base adjacent to the emitter. The gate is configured to accumulate the intrinsic base immediately under the gate dielectric layer, providing the band barrier at the top surface boundary of the intrinsic base.

公开(公告)号：US20170092748A1

公开(公告)日：2017-03-30

申请号：US15371801

申请日：2016-12-07

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yu-Wei Ting ,  Chun-Yang Tsai ,  Kuo-Ching Huang

IPC分类号： H01L29/732 ,  G11C13/00 ,  H01L27/24 ,  G11C11/16 ,  H01L29/66 ,  H01L27/22

CPC分类号： H01L29/732 ,  G11C11/161 ,  G11C11/40 ,  G11C13/0002 ,  G11C13/003 ,  G11C13/0069 ,  G11C2213/79 ,  H01L27/226 ,  H01L27/228 ,  H01L27/2436 ,  H01L27/2445 ,  H01L27/2454 ,  H01L29/66272 ,  H01L29/66333 ,  H01L29/82 ,  H01L45/04

摘要： Some aspects of this disclosure relate to a memory device. The memory device includes a collector region having a first conductivity type and which is coupled to a source line of the memory device. A base region is formed over the collector region and has a second conductivity type. A gate structure is coupled to the base region and acts as a shared word line for first and second neighboring memory cells of the memory device. First and second emitter regions are formed over the base region and have the first conductivity type. The first and second emitter regions are arranged on opposite sides of the gate structure. First and second contacts extend upwardly from the first and second emitter regions, respectively, and couple the first and second emitter regions to first and second data storage elements, respectively, of the first and second neighboring memory cells, respectively.

公开(公告)号：US20170018606A1

公开(公告)日：2017-01-19

申请号：US15278816

申请日：2016-09-28

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： KEVIN K. CHAN ,  BAHMAN HEKMATSHOARTABARI ,  TAK H. NING

IPC分类号： H01L29/06 ,  H01L29/167 ,  H01L29/66 ,  H01L29/735

CPC分类号： H01L29/0638 ,  H01L27/06 ,  H01L27/0623 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/167 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/66234 ,  H01L29/6625 ,  H01L29/66272 ,  H01L29/66287 ,  H01L29/732 ,  H01L29/735 ,  H01L29/7398

摘要： A method for forming a bipolar junction transistor includes forming a collector intrinsic region, an emitter intrinsic region and an intrinsic base region between the collector intrinsic region and the emitter intrinsic region. A collector extrinsic contact region is formed in direct contact with the collector intrinsic region; an emitter extrinsic contact region is formed on the emitter intrinsic region and a base extrinsic contact region is formed in direct contact with the intrinsic base region. Carbon is introduced into at least one of the collector extrinsic contact region, the emitter extrinsic contact region and the base extrinsic contact region to suppress diffusion of dopants into the junction region.

摘要翻译： 用于形成双极结型晶体管的方法包括在集电极本征区域和发射极本征区域之间形成集电极本征区域，发射极本征区域和本征基极区域。 集电体外部接触区域与集电极本征区域直接接触形成; 在发射极本征区域上形成发射极外部接触区域，并且形成与本征基极区域直接接触的基本非本征接触区域。 将碳引入到集电体外部本征接触区域，发射极非本征接触区域和基本非本征接触区域中的至少一个中，以抑制掺杂剂扩散到接合区域中。

公开(公告)号：US09508824B2

公开(公告)日：2016-11-29

申请号：US14556352

申请日：2014-12-01

申请人： IHP GmbH—Innovations for High Performance Microelectronics/Leibniz-Institut Fur Innovative Mikroelektronik

发明人： Alexander Fox ,  Bernd Heinemann ,  Steffen Marschmeyer

IPC分类号： H01L21/8249 ,  H01L29/66 ,  H01L21/8222 ,  H01L29/08 ,  H01L29/10 ,  H01L29/161 ,  H01L29/732 ,  H01L29/737

CPC分类号： H01L29/66242 ,  H01L21/8222 ,  H01L21/8249 ,  H01L29/0804 ,  H01L29/0817 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/161 ,  H01L29/66272 ,  H01L29/7322 ,  H01L29/7371

摘要： A method of producing a semiconductor device, comprising a substrate layer made of a semiconductor material of a first conductivity type and having a first insulation region, and a vertical bipolar transistor having a first vertical portion of a collector made of monocrystalline semiconductor material of a second conductivity type and disposed in an opening of the first insulation region, a second insulation region lying partly on the first vertical portion of the collector and partly on the first insulation region and having an opening in the region of the collector, in which opening a second vertical portion of the collector made of monocrystalline material is disposed, the portion including an inner region of the second conductivity type, a base made of monocrystalline semiconductor material of the first conductivity type, a base connection region surrounding the base in the lateral direction, a T-shaped emitter made of semiconductor material of the second conductivity type and overlapping the base connection region, wherein the base connection region, aside from a seeding layer adjacent the substrate or a metallization layer adjacent a base contact, consists of a semiconductor material which differs in its chemical composition from the semiconductor material of the collector, the base and the emitter and in which the majority charge carriers of the first conductivity type have greater mobility compared thereto.

摘要翻译： 一种制造半导体器件的方法，包括由第一导电类型的半导体材料制成并具有第一绝缘区域的衬底层和垂直双极晶体管，所述垂直双极晶体管具有由第二绝缘区域的单晶半导体材料制成的集电极的第一垂直部分 导电类型并且设置在第一绝缘区域的开口中，第二绝缘区域部分地位于集电体的第一垂直部分上并且部分地位于第一绝缘区域上，并且在集电体的区域中具有开口，其中开口第二绝缘区域 设置由单晶材料制成的集电体的垂直部分，该部分包括第二导电类型的内部区域，由第一导电类型的单晶半导体材料制成的基底，在横向方向上围绕基底的基底连接区域， 由第二导电类型的半导体材料制成的T形发射体及其结构 研磨基底连接区域，其中除了与基底相邻的接种层或与基底接触相邻的金属化层之外的基底连接区域由其化学组成与收集器的半导体材料不同的半导体材料组成，基底 并且其中与其相比，第一导电类型的多数电荷载流子具有更大的迁移率。

公开(公告)号：US20160254347A1

公开(公告)日：2016-09-01

申请号：US14633785

申请日：2015-02-27

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Hideaki Tsuchiko ,  Sik Lui

IPC分类号： H01L29/06 ,  H01L21/266 ,  H01L21/761

CPC分类号： H01L21/761 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/823878 ,  H01L21/823892 ,  H01L29/0619 ,  H01L29/063 ,  H01L29/0646 ,  H01L29/0692 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/1008 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/42368 ,  H01L29/6625 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/735 ,  H01L29/7816 ,  H01L29/7835 ,  H01L29/808

摘要： Aspects of the present disclosure provides a device comprising a P-type semiconductor substrate, an N-type tub above the semiconductor substrate, a P-type region provided in the N-type tub isolated by one or more P-type isolation structures, and an N-type punch-through stopper provided under the P-type regions isolated by the isolation structure(s). The punch-through stopper is heavily doped compared to the N-type tub. The P-type region has a width between the two isolation structures that is equal to or less than that of the N-type punch-through stopper.

摘要翻译： 本公开的方面提供了一种包括P型半导体衬底，在半导体衬底上的N型槽，设置在由一个或多个P型隔离结构隔离的N型槽中的P型区域的器件，以及 设置在由隔离结构隔离的P型区域下方的N型穿通止动件。 与N型槽相比，穿通止动器是重掺杂的。 P型区域的两个隔离结构之间的宽度等于或小于N型穿通止动件的宽度。

公开(公告)号：US09419087B2

公开(公告)日：2016-08-16

申请号：US14071239

申请日：2013-11-04

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Hsin Hu ,  Sun-Jay Chang ,  Min-Chang Liang ,  Shien-Yang Wu

IPC分类号： H01L29/735 ,  H01L29/423 ,  H01L27/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/732 ,  H01L21/8249

CPC分类号： H01L21/8249 ,  H01L27/0623 ,  H01L29/0692 ,  H01L29/1008 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/6625 ,  H01L29/66272 ,  H01L29/66795 ,  H01L29/732 ,  H01L29/735

摘要： A Bipolar Junction Transistor (BJT) includes an elongated collector line, an elongated emitter line parallel to the collector line, and an elongated base line parallel to the collector line and positioned between the collector line and the base line. The emitter line, the base line, and the collector line are formed over fin structures.

摘要翻译： 双极结晶体管（BJT）包括细长的收集线，平行于收集线的细长发射极线和平行于集电极线并位于收集线与基线之间的细长基线。 发射极线，基极线和集电极线形成在鳍结构之上。

公开(公告)号：US09419076B1

公开(公告)日：2016-08-16

申请号：US14563363

申请日：2014-12-08

申请人： Altera Corporation

发明人： Weimin Zhang ,  Yanzhong Xu

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/737 ,  H01L29/66 ,  H01L21/306 ,  H01L21/02 ,  H01L29/16 ,  H01L21/308 ,  H01L29/739 ,  H01L29/73

CPC分类号： H01L29/66795 ,  H01L21/3086 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/41708 ,  H01L29/66272 ,  H01L29/73 ,  H01L29/732 ,  H01L29/739 ,  H01L29/785

摘要： A bipolar junction transistor (BJT) is formed in a thin (less than about 20 nanometers) segment of a semiconductive material such as silicon where a lower portion of the semiconductive material has doping of a first conductivity type and forms a collector and an upper portion of the semiconductive material has doping of a second conductivity type and forms a base. Either a metal or a polysilicon emitter is formed on the base. An illustrative method for forming the BJT comprises forming first and second layers of a semiconductive material having first and second conductivity types, respectively; forming a hard mask on an upper surface of the second layer; using the hard mask to etch first and second channels in the semiconductive material on first and second opposing sides of the hard mask; removing the hard mask; and forming an emitter on the upper surface of the second layer.

摘要翻译： 双极结型晶体管（BJT）形成在诸如硅的半导体材料的薄（小于约20纳米）的段中，其中半导体材料的下部具有掺杂第一导电类型并形成集电极和上部 的半导体材料具有第二导电类型的掺杂并形成基底。 在基底上形成金属或多晶硅发射体。 用于形成BJT的说明性方法包括分别形成具有第一和第二导电类型的半导体材料的第一和第二层; 在第二层的上表面上形成硬掩模; 使用硬掩模来蚀刻硬掩模的第一和第二相对侧上的半导体材料中的第一和第二通道; 去除硬面膜; 以及在所述第二层的上表面上形成发射体。

公开(公告)号：US09397164B2

公开(公告)日：2016-07-19

申请号：US14944481

申请日：2015-11-18

申请人： Texas Instruments Incorporated

发明人： Brian E. Hornung ,  Xiang-Zheng Bo ,  Amitava Chatterjee ,  Alwin J. Tsao

IPC分类号： H01L29/10 ,  H01L27/06

CPC分类号： H01L29/1004 ,  H01L21/265 ,  H01L21/2652 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0821 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/66272 ,  H01L29/6659 ,  H01L29/732 ,  H01L29/7833

摘要： An integrated circuit and method having a deep collector vertical bipolar transistor with a first base tuning diffusion. A MOS transistor has a second base tuning diffusion. The first base tuning diffusion and the second base tuning diffusion are formed using the same implant.

摘要翻译： 一种集成电路和方法，其具有具有第一基极调谐扩散的深集电极垂直双极晶体管。 MOS晶体管具有第二基极调谐扩散。 第一基调谐扩散和第二基调谐扩散使用相同的植入物形成。

公开(公告)号：US20160197167A1

公开(公告)日：2016-07-07

申请号：US15073763

申请日：2016-03-18

申请人： International Business Machines Corporation

发明人： Joseph R. Greco ,  Qizhi Liu ,  Aaron L. Vallett ,  Robert F. Vatter

IPC分类号： H01L29/732 ,  H01L29/10 ,  H01L29/423 ,  H01L29/45 ,  H01L27/06 ,  H01L29/06 ,  H01L29/08

CPC分类号： H01L29/732 ,  H01L21/76232 ,  H01L21/76879 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0826 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/16 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/456 ,  H01L29/66234 ,  H01L29/66272 ,  H01L29/66287

摘要： Various particular embodiments include an integrated circuit (IC) structure having: a stack region; and a silicon substrate underlying and contacting the stack region, the silicon substrate including: a silicon region including a doped subcollector region; a set of isolation regions overlying the silicon region; a base region between the set of isolation regions and below the stack region, the base region including an intrinsic base contacting the stack region, an extrinsic base contacting the intrinsic base and the stack region, and an amorphized extrinsic base contact region contacting the extrinsic base; a collector region between the set of isolation regions; an undercut collector-base region between the set of isolation regions and below the base region; and a collector contact region contacting the collector region under the intrinsic base and the collector-base region via the doped subcollector region.

摘要翻译： 各种具体实施例包括具有堆叠区域的集成电路（IC）结构; 以及位于所述堆叠区域下方并接触的硅衬底，所述硅衬底包括：包含掺杂子集电极区域的硅区域; 一组覆盖硅区的隔离区; 所述基极区域在所述隔离区域之间并且在所述堆叠区域之下，所述基极区域包括与所述堆叠区域接触的本征基极，与所述本征基极和所述堆叠区域接触的非本征基极，以及接触所述外部基极的非晶化非本征基极接触区域 ; 在所述一组隔离区域之间的集电极区域; 在所述一组隔离区域和所述基底区域之下的底切集电极 - 基极区域; 以及通过掺杂子集电极区域与本征基极之下的集电极区域和集电极 - 基极区域接触的集电极接触区域。

公开(公告)号：US20160190277A1

公开(公告)日：2016-06-30

申请号：US15063541

申请日：2016-03-08

申请人： Infineon Technologies Dresden GmbH

发明人： Dmitri Alex Tschumakow ,  Claus Dahl ,  Armin Tilke

IPC分类号： H01L29/66 ,  H01L29/10 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L21/265 ,  H01L21/324 ,  H01L29/165 ,  H01L29/08 ,  H01L29/417

CPC分类号： H01L29/66272 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/26513 ,  H01L21/324 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/165 ,  H01L29/41708 ,  H01L29/42304 ,  H01L29/66242 ,  H01L29/66287 ,  H01L29/732 ,  H01L29/7371 ,  H01L29/7378

摘要： According to various embodiments, a bipolar transistor structure may include: a substrate; a collector region in the substrate; a base region disposed over the collector region, an emitter region disposed over the base region; a base terminal laterally electrically contacting the base region, wherein the base terminal includes polysilicon.