公开(公告)号：US3963524A

公开(公告)日：1976-06-15

申请号：US594341

申请日：1975-07-09

申请人： Juergen Graul ,  Helmuth Murrmann

发明人： Juergen Graul ,  Helmuth Murrmann

IPC分类号： H01L29/73 ,  H01L21/00 ,  H01L21/033 ,  H01L21/22 ,  H01L21/265 ,  H01L21/266 ,  H01L21/311 ,  H01L21/331 ,  H01L29/732

CPC分类号： H01L29/7325 ,  H01L21/00 ,  H01L21/033 ,  H01L21/31111

摘要： The surface of a semiconductor substrate, such as a silicon crystal, is uniformly coated with a layer of Si.sub.3 N.sub.4 and at least two selectively spaced windows are provided therein. The uncovered silicon surface within such windows is then coated with a layer of SiO.sub.2. Next, a SiO.sub.2 area within a first window along with a portion of the adjacent Si.sub.3 N.sub.4 areas are coated with a photo-lacquer mask while the substrate surface area beneath the second window is doped with a select dopant. This procedure is then reversed and the Photo-lacquer mask is removed from the first window and applied onto the second window while the substrate surface area beneath the first window is contacted with select dopant to produce a doped zone. In this manner, considerable tolerance for positioning of a diffusion mask is provided.

摘要翻译： 诸如硅晶体的半导体衬底的表面均匀地涂覆有Si 3 N 4层，并且在其中提供至少两个选择性间隔的窗口。 然后在这种窗口内的未覆盖的硅表面涂覆有一层SiO 2。 接下来，在第一窗口内的SiO 2区域与相邻的Si 3 N 4区域的一部分一起涂覆有光漆掩模，同时第二窗口下面的衬底表面区域掺杂有选择掺杂剂。 然后将该过程反转，并且从第一窗口移除光漆掩模并施加到第二窗口上，同时第一窗口下方的基板表面区域与选择掺杂剂接触以产生掺杂区域。 以这种方式，提供了用于定位扩散掩模的相当大的容限。

公开(公告)号：US3753802A

公开(公告)日：1973-08-21

申请号：US3753802D

申请日：1964-03-05

申请人： PHILIPS CORP

发明人： TUMMERS L

IPC分类号： C30B25/02 ,  H01L21/00 ,  H01L21/18 ,  H01L21/203 ,  H01L21/205 ,  H01L29/00 ,  H01L29/732 ,  H01L7/36

CPC分类号： H01L29/7325 ,  C30B25/02 ,  H01L21/00 ,  H01L21/185 ,  H01L29/00

摘要： A method of making a transistor by forming a layer of high resistivity on a semiconductor collector body, diffusing a base zone into the layer to a depth less than the thickness of the layer and then forming an emitter zone in the base zone.

摘要翻译： 一种通过在半导体集热体上形成高电阻率层来制造晶体管的方法，将基底区域扩散到该层的深度以下，然后在该基区中形成发射区。

公开(公告)号：US3648123A

公开(公告)日：1972-03-07

申请号：US3648123D

申请日：1970-02-19

申请人： FREDERICK G ERNICK ,  THORNDIKE C T NEW ,  DONALD A WALCZAK

发明人： ERNICK FREDERICK G ,  NEW THORNDIKE C T ,  WALCZAK DONALD A

IPC分类号： H01L23/31 ,  H01L29/00 ,  H01L29/732 ,  H01L9/12 ,  H01L11/06

CPC分类号： H01L29/7325 ,  H01L23/3157 ,  H01L29/00 ,  H01L2924/0002 ,  Y10S148/026 ,  Y10S148/036 ,  Y10S148/049 ,  Y10S148/051 ,  Y10S148/085 ,  Y10S148/122 ,  H01L2924/00

摘要： An improved high-speed PNP power transistor, either planar or mesa, comprises at least two epitaxial layers, on a lowresistivity P-type substrate, a first epitaxial layer on the substrate being P-, to provide a collector, and a second epitaxial layer is N-type to provide a base and has an N+ surface layer not exceeding about 1 micron in thickness and of a resistance of about 0.01 ohm-cm., to provide for low saturation, and a P-type emitter laterally contacting or abutting the lowsaturation layer, the P-type emitter being either an epitaxially deposited layer to provide a mesa configuration or produced by diffusion through the second epitaxial layer entirely through the saturation surface, in either case to provide a base width of between 1.2 to 4.5 microns.

摘要翻译： 改进的高速PNP功率晶体管（平面或台面）在低电阻率P型衬底上包括至少两个外延层，衬底上的第一外延层为P-，以提供集电极，并且第二 外延层是N型以提供基底并且具有不超过约1微米厚度的N +表面层和约0.01欧姆 - 厘米的电阻以提供低饱和度，并且P型发射体横向接触或 邻近低饱和层，P型发射体是外延沉积层，以提供台面构型，或通过扩散通过第二外延层通过饱和表面产生，在任一情况下，提供介于1.2至1.2之间的基极宽度 4.5微米。

公开(公告)号：US3639815A

公开(公告)日：1972-02-01

申请号：US3639815D

申请日：1969-09-30

申请人： WESTINGHOUSE ELECTRIC CORP

发明人： ERNICK FREDERICK G ,  KISINKO PAUL M ,  MARINO JOSEPH ,  KANNAM PETER J

IPC分类号： H01L23/31 ,  H01L29/00 ,  H01L29/732 ,  H01L11/06

CPC分类号： H01L29/7325 ,  H01L23/3157 ,  H01L29/00 ,  H01L2924/0002 ,  Y10S148/026 ,  Y10S148/036 ,  Y10S148/049 ,  Y10S148/051 ,  Y10S148/085 ,  Y10S148/122 ,  H01L2924/00

摘要： A transistor having an epitaxially grown base region has the good secondary breakdown voltage performance of a single diffused transistor having a base region comprising suitably doped material having a uniform level of impurity concentration as well as all of the desirable frequency response benefits achieved by epitaxially formed transistors.

摘要翻译： 具有外延生长的基极区域的晶体管具有具有包括具有均匀杂质浓度水平的适当掺杂材料的基极区域的单个扩散晶体管的良好二次击穿电压性能以及通过外延形成的晶体管实现的所有所需的频率响应益处 。

公开(公告)号：US20240047398A1

公开(公告)日：2024-02-08

申请号：US18489540

申请日：2023-10-18

申请人： Murata Manufacturing Co., Ltd.

发明人： Atsushi KUROKAWA ,  Mari SAJI

IPC分类号： H01L23/00 ,  H01L29/737 ,  H01L29/73 ,  H01L29/732 ,  H01L25/065

CPC分类号： H01L24/13 ,  H01L24/29 ,  H01L29/737 ,  H01L29/7317 ,  H01L29/7325 ,  H01L25/0657 ,  H01L2924/13051 ,  H01L2225/06517 ,  H01L2924/014 ,  H01L2224/1302 ,  H01L2224/13007 ,  H01L2224/29022 ,  H01L2224/29005

摘要： A semiconductor device includes a semiconductor substrate; at least one first transistor, each first transistor including a mesa structure including one or more semiconductor layers; a first bump overlapping the first transistors and extending in a first direction; and a second bump. The mesa structure includes a first end portion at one end in a second direction and a second end portion at another end in the second direction. In plan view, an outer periphery of the first bump includes a first side and a second side extending in the first direction and arranged next to each other in the second direction. The first side is closer to the second bump than the second side in the second direction. The first end portion and the second end portion of the mesa structure are between the first side and the second side.

公开(公告)号：US20230318543A1

公开(公告)日：2023-10-05

申请号：US18328653

申请日：2023-06-02

申请人： Murata Manufacturing Co., Ltd.

发明人： Shigeki KOYA ,  Shaojun MA ,  Shinnosuke TAKAHASHI

IPC分类号： H03F3/21 ,  H01L29/732

CPC分类号： H03F3/21 ,  H01L29/7325 ,  H03F2200/451

摘要： A power amplifier comprising amplifier circuits of multiple stages. Each of the amplifier circuits of multiple stages includes a bipolar transistor and a base electrode. The bipolar transistor included in each of the amplifier circuits of multiple stages includes a collector layer, a base layer placed on the collector layer, and an emitter mesa placed on part of the region of the base layer. The emitter mesa has a shape elongated in one direction in plan view. The base electrode includes a base main portion arranged in such a manner as to be separated from the emitter mesa with a gap in a direction orthogonal to a lengthwise direction of the emitter mesa in plan view. The base main portion has a shape elongated in a direction parallel to the lengthwise direction of the emitter mesa in plan view and is electrically connected to the base layer.

公开(公告)号：US20190007041A1

公开(公告)日：2019-01-03

申请号：US16011909

申请日：2018-06-19

申请人： FRAUNHOFER-GESELLSCHAFT ZUR FOERDERUNG DER ANGEWANDTEN FORSCHUNG E.V.

发明人： TOBIAS ERLBACHER ,  Stefan Matlok

IPC分类号： H03K17/16 ,  H02M1/34 ,  H03K17/0814 ,  H01L29/78

CPC分类号： H03K17/687 ,  H01L27/0727 ,  H01L28/20 ,  H01L29/0821 ,  H01L29/407 ,  H01L29/732 ,  H01L29/7325 ,  H01L29/7408 ,  H01L29/7803 ,  H01L29/8083 ,  H01L29/945 ,  H02M2001/322 ,  H02M2001/344

摘要： The present invention relates to an electrical circuit arrangement with an active discharge circuit including at least one electrical switching element, by means of which the circuit arrangement can be discharged in controlled manner. The circuit arrangement includes a RC snubber element with capacitor and resistor for damping voltage or current peaks in the circuit arrangement, wherein the electrical switching element is integrated in the RC snubber element and connected in parallel to the capacitor of the RC snubber. This enables the discharge circuit to be designed in a manner that is economical in terms of space and cost. The discharge circuit uses the heat sink for the RC snubber element and therefore does not need any additional heat dissipation systems.

公开(公告)号：US20180337233A1

公开(公告)日：2018-11-22

申请号：US15959295

申请日：2018-04-23

申请人： FUJI ELECTRIC CO., LTD.

发明人： Tatsuya NAITO

IPC分类号： H01L29/08 ,  H01L29/732 ,  H01L29/739 ,  H01L29/66 ,  H01L29/417

CPC分类号： H01L29/0804 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/407 ,  H01L29/41708 ,  H01L29/4238 ,  H01L29/66545 ,  H01L29/7325 ,  H01L29/7396 ,  H01L29/7397

摘要： A semiconductor device includes: a gate trench portion and a dummy trench portion provided extending in a predetermined direction of extension at the upper surface of the semiconductor substrate; a mesa portion sandwiched by the gate trench portion and the dummy trench portion; an emitter region provided between the upper surface of the semiconductor substrate and the drift region and provided at an upper surface of the mesa portion and adjacent to the gate trench portion; and a contact region provided between the upper surface of the semiconductor substrate and the drift region and provided at the upper surface of the mesa portion and adjacent to the dummy trench portion, wherein at least either the emitter region or the contact region is provided in a stripe shape extending in the direction of extension at the upper surface of the semiconductor substrate.

公开(公告)号：US09245951B1

公开(公告)日：2016-01-26

申请号：US14487582

申请日：2014-09-16

申请人： GLOBALFOUNDRIES INC.

发明人： Renata Camillo-Castillo ,  David L. Harame ,  Vibhor Jain ,  Vikas K. Kaushal ,  Marwan H. Khater

IPC分类号： H01L21/331 ,  H01L29/08 ,  H01L29/732 ,  H01L29/66 ,  H01L29/10

CPC分类号： H01L29/0826 ,  H01L21/31056 ,  H01L21/31111 ,  H01L21/31144 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66234 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/7325 ,  H01L29/7378

摘要： Device structures and fabrication methods for a bipolar junction transistor. A layer is formed on a top surface of a substrate. A trench is formed in the layer and has a plurality of sidewalls with a width between an opposite pair of the sidewalls that varies with increasing distance from the top surface of the substrate. A collector pedestal of the bipolar junction transistor is formed in the trench.

摘要翻译： 双极结型晶体管的器件结构和制造方法。 在衬底的顶表面上形成一层。 在该层中形成沟槽并且具有多个侧壁，其宽度在相对的一对侧壁之间的宽度随着距离衬底顶表面的距离的增加而变化。 在沟槽中形成双极结型晶体管的集电极基座。

公开(公告)号：US20140291681A1

公开(公告)日：2014-10-02

申请号：US14223008

申请日：2014-03-24

申请人： SKYWORKS SOLUTIONS, INC.

发明人： Stephen Joseph KOVACIC

IPC分类号： H01L29/735 ,  H01L29/04 ,  H01L29/66

CPC分类号： H01L29/7325 ,  H01L29/1004 ,  H01L29/66287

摘要： Semiconductor devices are disclosed having modified transistor dimensions configured to provide reduced phase noise in certain amplifier applications. Transistor devices having expanded emitter-poly overlap of the emitter window, which serves to separate the external base area from the lateral emitter-base junction, may experience a reduction of free electrons and holes that diffuse into the electric field of the emitter-base junction, thereby reducing phase noise.

摘要翻译： 公开了具有修改的晶体管尺寸的半导体器件，其被配置为在某些放大器应用中提供降低的相位噪声。 具有用于将外部基极区域与侧向发射极 - 基极结分离的发射器窗口的发射极 - 多重重叠的发射极 - 多重叠的晶体管器件可能经历扩散到发射极 - 基极结的电场中的自由电子和空穴的减少 ，从而减少相位噪声。