公开(公告)号：US09306844B2

公开(公告)日：2016-04-05

申请号：US13673505

申请日：2012-11-09

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Riccardo Locatelli ,  Esa Petri ,  Antonio-Marcello Coppolla ,  Luca Fanucci ,  Sergio Saponara ,  Tony Bacchillone

IPC: H04L12/28 ,  H04L12/741 ,  H04L12/775 ,  H04L12/931 ,  H04L12/933 ,  H04L12/721 ,  H04L12/773

CPC classification number: H04L45/74 ,  H04L45/34 ,  H04L45/58 ,  H04L45/60 ,  H04L49/109 ,  H04L49/70

Abstract: A router includes a plurality of virtual networks, a plurality of output links, at least one decoder and arbitration circuitry. Each virtual network has a plurality of virtual network inputs and a plurality of virtual network outputs. Each virtual network output is associated with an output link. The decoder decodes a header of a data unit received on a virtual network of one of the virtual network inputs. The decoder generates a first request and a second request. The first request is for the allocation of a virtual network output of the virtual network to the virtual network input. The second request is for the allocation of an output link associated with the virtual network output to the virtual network output. The arbitration circuitry performs arbitration of the first request and arbitration of the second request in parallel.

Abstract translation: 路由器包括多个虚拟网络，多个输出链路，至少一个解码器和仲裁电路。 每个虚拟网络具有多个虚拟网络输入和多个虚拟网络输出。 每个虚拟网络输出与输出链路相关联。 解码器解码在虚拟网络输入之一的虚拟网络上接收的数据单元的报头。 解码器产生第一请求和第二请求。 第一个请求是将虚拟网络的虚拟网络输出分配给虚拟网络输入。 第二个请求是将与虚拟网络输出相关联的输出链路分配给虚拟网络输出。 仲裁电路并行执行第一请求的仲裁和第二请求的仲裁。

公开(公告)号：US09299733B2

公开(公告)日：2016-03-29

申请号：US14660404

申请日：2015-03-17

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Flavien Hirigoyen

IPC: H01L27/146 ,  H01L31/0232

CPC classification number: H01L27/14625 ,  H01L27/14605 ,  H01L27/14629

Abstract: An image sensor is formed by a pixel array including a plurality of pixels. Certain ones of the pixels include, above their active areas, a first optical grating formed of periodically spaced apart parallel strips separated from the active area by a first insulator. Those pixels further include, in another metal level, a second optical grating formed of periodically spaced apart parallel strips separated from the first grating by a second insulator. The second optical grating is laterally shifted with respect to the first grating in a direction orthogonal to a longitudinal direction of the parallel strips.

Abstract translation: 图像传感器由包括多个像素的像素阵列形成。 像素中的某些像素包括在它们的有效区域上方的由第一绝缘体与有源区分开的周期性间隔开的平行条形成的第一光栅。 这些像素还包括在另一金属层中的由第二绝缘体与第一光栅隔开的周期性间隔开的平行条形成的第二光栅。 第二光栅相对于第一光栅在与平行条的纵向方向正交的方向上横向偏移。

公开(公告)号：US20160080722A1

公开(公告)日：2016-03-17

申请号：US14953938

申请日：2015-11-30

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS

Inventor： FRANKIE EYMARD ,  JEAN-LOUIS LABYRE

IPC: H04N13/00

CPC classification number: H04N13/194 ,  H04N7/24 ,  H04N13/10 ,  H04N13/106 ,  H04N13/161 ,  H04N19/16 ,  H04N2013/0088

Abstract: The present disclosure relates to a method for transmitting two consecutive pairs of images. The method may include decimating each image with a ratio of 2, assembling the two decimated images of each pair in a composite image, transmitting the composite images, and reconstructing complete images from the composite images. In decimation, the information removed from the images of the first pair may be kept in the images of the second pair, from the spatial point of view, and the complete images may be reconstructed by de-interlacing processing from the composite images.

公开(公告)号：US20160079291A1

公开(公告)日：2016-03-17

申请号：US14744482

申请日：2015-06-19

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Alps) SAS

Inventor： Nicolas Moeneclaey ,  Julien-Marc Roux ,  Jerome Bourgoin

IPC: H01L27/146 ,  H04N5/374 ,  H04N5/378

CPC classification number: H01L27/14612 ,  H01L27/14643 ,  H04N5/367 ,  H04N5/374 ,  H04N5/3742 ,  H04N5/3745 ,  H04N5/378 ,  H04N17/002

Abstract: A CMOS image sensor including: an array of M×N pixels, the pixels of a same column being connected to a same output track, each pixel including a photodiode, a sense node, a transfer transistor, a reset transistor, and a read circuit; and a test circuit including an assembly of N elementary reference cells respectively connected to the N output tracks of the sensor, each cell including a resistor, a sense node, a transfer transistor, a reset transistor, and a read circuit, the N resistors being series-connected between first and second nodes of application of a reference voltage.

Abstract translation: 一种CMOS图像传感器，包括：M×N个像素的阵列，同一列的像素连接到相同的输出轨道，每个像素包括光电二极管，感测节点，传输晶体管，复位晶体管和读取电路 ; 以及测试电路，其包括分别连接到所述传感器的N个输出轨道的N个基本参考单元的组合，每个单元包括电阻器，感测节点，传输晶体管，复位晶体管和读取电路，所述N个电阻器 串联连接在施加参考电压的第一和第二节点之间。

公开(公告)号：US09184138B2

公开(公告)日：2015-11-10

申请号：US13719103

申请日：2012-12-18

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics S.r.l.

Inventor： Angelo Antonio Merassi ,  Marco Ferrera ,  Marco Mantovani ,  Paolo Ferrari ,  Benedetto Vigna

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/16 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L21/56 ,  H01L23/16 ,  H01L23/3107 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor integrated device is provided with: a die having a body of semiconductor material with a front surface, and an active area arranged at the front surface; and a package having a support element carrying the die at a back surface of the body, and a coating material covering the die. The body includes a mechanical decoupling region, which mechanically decouples the active area from mechanical stresses induced by the package; the mechanical decoupling region is a trench arrangement within the body, which releases the active area from an external frame of the body, designed to absorb the mechanical stresses induced by the package.

Abstract translation: 半导体集成器件具有：具有前表面的半导体材料体的主体和配置在前表面的有源区域; 以及具有在主体的背面承载模具的支撑元件和覆盖模具的包覆材料的包装。 机体包括机械解耦区域，机械解耦有源区域与由包装引起的机械应力; 机械解耦区域是主体内的沟槽布置，其从主体的外框架释放活动区域，设计成吸收由包装引起的机械应力。

公开(公告)号：US20150248934A1

公开(公告)日：2015-09-03

申请号：US14635815

申请日：2015-03-02

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Vincent Rabary ,  Nicolas Aupetit

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C11/5664 ,  G11C13/0002 ,  G11C13/004 ,  G11C13/0097 ,  G11C17/165 ,  G11C17/18 ,  G11C2013/0054

Abstract: A non-volatile digital memory includes: a plurality of thin film resistors; and a control circuit adapted to: program, during a first programming phase, the thin film resistors with a plurality of bits of data by passing a current through at least one of the thin film resistors to reduce its resistance; and read, during a restoration phase, the plurality of bits of data stored by the thin film resistors by generating an electrical signal associated with each thin film resistor and comparing each electrical signal with a reference signal.

Abstract translation: 非挥发性数字存储器包括：多个薄膜电阻器; 以及控制电路，适于：在第一编程阶段期间，通过使电流通过至少一个薄膜电阻器来减小其电阻，来编制具有多个数据位的薄膜电阻器; 并且在恢复阶段期间通过产生与每个薄膜电阻器相关联的电信号并且将每个电信号与参考信号进行比较来读取由薄膜电阻器存储的多个数据位。

公开(公告)号：US09105766B2

公开(公告)日：2015-08-11

申请号：US13845445

申请日：2013-03-18

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics Pte Ltd

Inventor： Romain Coffy ,  Eric Saugier ,  Hk Looi ,  Norbert Chevrier

IPC: H01L33/48 ,  H01L31/0203 ,  H01L31/18 ,  G01S17/02 ,  H01L25/16 ,  H03K17/94 ,  G01S7/481 ,  H03K17/945

CPC classification number: H01L31/0203 ,  G01S7/481 ,  G01S17/026 ,  H01L25/167 ,  H01L31/18 ,  H01L2224/48091 ,  H01L2224/49175 ,  H01L2924/181 ,  H03K17/941 ,  H03K2017/9455 ,  H03K2217/94026 ,  H03K2217/94112 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: An optical electronic package includes transmitting chip and a receiving chip fixed to a wafer. A transparent encapsulation structure is formed by a transparent plate and a transparent encapsulation block that are formed over the transmitter chip and at least a portion of the receiver chip, with the transparent encapsulation block embedding the transmitter chip. An opaque encapsulation block extends over the transparent plate and includes an opening that reveals a front area of the transparent plate. The front area is situated above an optical transmitter of the transmitting chip and is offset laterally relative to an optical sensor of the receiving chip.

Abstract translation: 光学电子封装包括固定到晶片的透射芯片和接收芯片。 透明封装结构由形成在发射机芯片和接收芯片的至少一部分上的透明板和透明封装块形成，透明封装块嵌入发射器芯片。 不透明的封装块在透明板上延伸并且包括露出透明板的前部区域的开口。 前部区域位于发射芯片的光发射机之上，相对于接收芯片的光学传感器横向偏移。

公开(公告)号：US20150213777A1

公开(公告)日：2015-07-30

申请号：US14607523

申请日：2015-01-28

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Marina Nicolas

IPC: G09G5/00 ,  G06T3/40

CPC classification number: G09G5/005 ,  G06T3/0012 ,  G06T3/40 ,  G09G2340/0442

Abstract: A source image is transformed into a destination image having a target aspect ratio. A reference region in the source image is defined. An extended region of interest of the source image having the target aspect ratio and containing the reference region is defined. A set of candidate image regions of increasing resolutions from the extended region of interest is determined, each having the target aspect ratio and containing the reference region. Candidate image regions are scaled to form a candidate target images. A quality metric is used to select a target image providing the best quality metric value.

Abstract translation: 源图像被转换成具有目标纵横比的目标图像。 定义源图像中的参考区域。 定义具有目标纵横比并包含参考区域的源图像的扩展区域。 确定从感兴趣的扩展区域增加分辨率的一组候选图像区域，每一个具有目标纵横比并且包含参考区域。 缩放候选图像区域以形成候选目标图像。 使用质量度量来选择提供最佳质量度量值的目标图像。

公开(公告)号：US20150115424A1

公开(公告)日：2015-04-30

申请号：US14524906

申请日：2014-10-27

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Jean-Michel Riviere ,  Nadine Martin

IPC: H01L23/495 ,  H01L25/065

CPC classification number: H01L25/0657 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/49816 ,  H01L23/5389 ,  H01L25/105 ,  H01L2023/4056 ,  H01L2023/4062 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An electronic system includes a first electronic device (with a first integrated-circuit chip) and a second electronic device (with a second integrated-circuit chip). The second electronic device is stacked above the first electronic device on a same side as the first integrated-circuit chip. Electrical connection elements located around the first integrated-circuit chip electrically connected to the second electronic device to the first electronic device. A metal plate configured for heat capture and transfer extends between the first and second electronic devices. The metal plate includes through-passages aligned to permit the electrical connection elements to pass at a distance.

Abstract translation: 电子系统包括第一电子设备（具有第一集成电路芯片）和第二电子设备（具有第二集成电路芯片）。 第二电子装置在与第一集成电路芯片相同的一侧堆叠在第一电子装置的上方。 电连接元件围绕第一集成电路芯片电连接到第二电子设备到第一电子设备。 配置用于捕获和传送的金属板在第一和第二电子设备之间延伸。 金属板包括对准以允许电连接元件一段距离通过的通孔。

公开(公告)号：US20150102500A1

公开(公告)日：2015-04-16

申请号：US14512060

申请日：2014-10-10

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Romain Coffy ,  Rémi Brechignac

IPC: H01L23/00 ,  H01L23/522

CPC classification number: H01L24/33 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5226 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2224/32146 ,  H01L2224/32225 ,  H01L2224/32235 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06575 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H05K1/144 ,  H01L2924/00012 ,  H01L2924/00

Abstract: An electronic system includes a first integrated-circuit chip and a second integrated-circuit chip. A first substrate wafer is positioned between the first and second integrated-circuit chips and configured with a first connection network to make electrical connection to the first integrated-circuit chip. A second substrate wafer, configured with a second connection network to make electrical connection to the second integrated-circuit chip, is positioned facing the first substrate wafer. The connection networks of the first and second substrate wafers are electrically connected through connection structures. A third substrate wafer, including a third connection network, is thermally in contact with the first integrated-circuit chip and electrically connected to the first connection network of the first substrate wafer through further connection structures. The further connection structure may be formed using another substrate wafer.

Abstract translation: 电子系统包括第一集成电路芯片和第二集成电路芯片。 第一衬底晶片位于第一和第二集成电路芯片之间并且配置有第一连接网络以与第一集成电路芯片进行电连接。 配置有与第二集成电路芯片进行电连接的第二连接网络的第二衬底晶片被定位成面向第一衬底晶片。 第一和第二衬底晶片的连接网络通过连接结构电连接。 包括第三连接网络的第三衬底晶片与第一集成电路芯片热接触，并通过另外的连接结构电连接到第一衬底晶片的第一连接网络。 另外的连接结构可以使用另一个衬底晶片形成。