公开(公告)号：US20200351038A1

公开(公告)日：2020-11-05

申请号：US16861164

申请日：2020-04-28

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Richard E. Perego ,  Craig E. Hampel

IPC: H04L1/24 ,  H04L7/00 ,  H04L7/10 ,  H04L25/02 ,  H04L25/12 ,  G11C29/02 ,  G11C7/10 ,  H04L27/00

Abstract: A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.

公开(公告)号：US10811062B2

公开(公告)日：2020-10-20

申请号：US16528523

申请日：2019-07-31

Applicant: Rambus Inc.

Inventor： James E. Harris ,  Thomas Vogelsang ,  Frederick A. Ware ,  Ian P. Shaeffer

IPC: G11C7/00 ,  G11C7/10 ,  G11C7/08 ,  G11C5/02 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4091 ,  G11C7/06 ,  G11C7/12 ,  G11C7/22 ,  G11C8/08 ,  G11C8/10

Abstract: Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.

公开(公告)号：US20200294577A1

公开(公告)日：2020-09-17

申请号：US16825247

申请日：2020-03-20

Applicant: Rambus Inc.

Inventor： Wayne F. Ellis ,  Wayne S. Richardson ,  Akash Bansal ,  Frederick A. Ware ,  Lawrence Lai ,  Kishore Ven Kasamsetty

IPC: G11C11/406 ,  G11C7/02 ,  G11C7/20 ,  G11C11/4072 ,  G11C29/02 ,  G06F1/3234 ,  G11C11/4074

Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.

公开(公告)号：US10762948B2

公开(公告)日：2020-09-01

申请号：US15829787

申请日：2017-12-01

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Zhichao Lu ,  Kenneth Lee Wright

IPC: G11C11/34 ,  G11C11/4091 ,  G06F11/10 ,  G11C11/4076

Abstract: Memory devices, controllers and associated methods are provided. In one embodiment, a memory device is provided. The memory device includes storage cells that are each formed with a metal-oxide-semiconductor (MOS) transistor having a floating body. Data is stored as charge in the floating body. A transfer interface receives a read command to access data stored in a first group of the storage cells. Sensing circuitry detects the data stored in the first group of storage cells. The transfer interface selectively performs a writeback operation of the sensed data associated with the read command.

公开(公告)号：US10761587B2

公开(公告)日：2020-09-01

申请号：US16193247

申请日：2018-11-16

Applicant: RAMBUS INC.

Inventor： Dinesh Patil ,  Amir Amirkhany ,  Farrukh Aquil ,  Kambiz Kaviani ,  Frederick A. Ware

IPC: G06F1/324 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4093 ,  G11C11/4076 ,  G06F1/3234 ,  G06F1/3287 ,  G06F5/06 ,  G11C7/04 ,  H03L7/081

Abstract: Embodiments generally relate to a memory device. In one embodiment, the memory device includes a clock receiver circuit that receives an external clock signal and provides an internal clock signal. The memory device also includes a delay-locked loop circuit (DLL) having an input, and a circuit that receives the internal clock signal. The circuit selects which pulses of the internal clock signal are applied to the input of the DLL, such that no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval. In another embodiment, a method includes receiving an external clock signal at a clock receiver circuit, receiving an internal clock signal from the clock receiver circuit, and selecting which pulses of the internal clock signal are applied to an input of a DLL, where no more than two clock pulses selected from at least three consecutive pulses of the external clock signal are applied to the input of the DLL during a predetermined interval.

公开(公告)号：US10757835B2

公开(公告)日：2020-08-25

申请号：US15783949

申请日：2017-10-13

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Carl W. Werner

IPC: H05K7/20 ,  G06F1/20 ,  H01L27/108 ,  G06F1/18 ,  H01B7/29 ,  H01B7/04 ,  H01L23/522 ,  H01L23/532 ,  H01L23/367 ,  H01L23/498 ,  H01B3/12 ,  H01B1/02 ,  H01L23/538

Abstract: The embodiments herein describe technologies of cryogenic digital systems with a first component located in a first cryogenic temperature domain and a second component located in a second cryogenic temperature domain that is lower in temperature than the first cryogenic temperature domain. An electrical conductor is coupled between the first component and the second component along a first plane. The electrical conductor carries a signal between the first component and the second component. A cooling assembly is coupled to a segment of the electrical conductor. The cooling assembly may include an electrical insulator including ceramic material. The cooling assembly may include a cold plate, two cold plates, or an orthogonal cold strip.

公开(公告)号：US20200258555A1

公开(公告)日：2020-08-13

申请号：US16790183

申请日：2020-02-13

Applicant: Rambus Inc.

Inventor： Richard E. Perego ,  Frederick A. Ware

IPC: G11C7/10 ,  G06F13/16 ,  G11C5/06

Abstract: A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The number of request ports per memory device and the data width of each memory device changes with the number of memory devices such that the ratio of the request-access granularity to the data granularity remains constant irrespective of the number of memory devices.

公开(公告)号：US20200257589A1

公开(公告)日：2020-08-13

申请号：US16790637

申请日：2020-02-13

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Brent Haukness

IPC: G06F11/10 ,  G06F12/02 ,  G11C29/52

Abstract: A memory device is disclosed that includes a row of storage locations that form plural columns. The plural columns include data columns to store data and a tag column to store tag information associated with error locations in the data columns. Each data column is associated with an error correction location including an error code bit location. Logic retrieves and stores the tag information associated with the row in response to activation of the row. A bit error in an accessed data column is repaired by a spare bit location based on the tag information.

公开(公告)号：US10725099B2

公开(公告)日：2020-07-28

申请号：US16357122

申请日：2019-03-18

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G01R31/28 ,  G01R31/317 ,  G11C29/02 ,  G11C29/12 ,  G11C29/16 ,  G11C29/50 ,  G01R31/26 ,  H03L7/00 ,  G11C29/04

Abstract: A memory controller instantiated on a semiconductor IC device comprises a timing circuit to transfer a timing signal, the timing circuit being configured to receive a first test signal and to effect a delay in the timing signal in response to the first test signal, the first test signal including a first timing event. The memory controller further comprises an interface circuit configured to transfer the data signal in response to the timing signal, the interface circuit being further configured to receive a second test signal and to effect a delay in the data signal in response to the second test signal, the second test signal including a second timing event that is related to the first timing event according to a test criterion.

公开(公告)号：US10678719B2

公开(公告)日：2020-06-09

申请号：US15761746

申请日：2016-09-09

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Kenneth L. Wright ,  John Eric Linstadt ,  Craig Hampel

IPC: G06F13/16 ,  G06F12/0868 ,  G06F12/0888 ,  G11C7/10 ,  G06F3/06 ,  G06F11/10 ,  G06F12/0895 ,  G06F13/28 ,  G11C29/52

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, a memory module includes a pin interface for coupling to a bus. The bus has a first width. The module includes at least one storage class memory (SCM) component and at least one DRAM component. The memory module operates in a first mode that utilizes all of the first width, and in a second mode that utilizes less than all of the first width.