公开(公告)号：US07351638B1

公开(公告)日：2008-04-01

申请号：US10021782

申请日：2001-12-18

Applicant: Cyrus E. Tabery ,  Eric N. Paton ,  Bin Yu ,  Qi Xiang ,  Robert B. Ogle

Inventor： Cyrus E. Tabery ,  Eric N. Paton ,  Bin Yu ,  Qi Xiang ,  Robert B. Ogle

IPC: H01L21/336

CPC classification number: H01L21/268 ,  H01L21/26513 ,  H01L29/6659

Abstract: A method of manufacturing a semiconductor device includes forming a gate electrode over a substrate, implanting dopants into the substrate and activating the dopants using laser thermal annealing. During annealing, the laser and substrate are moved relative to one another, and the movement of the laser and the substrate relative to one another does not pause between and during activating one portion of the source/drain regions and activating another portion of the source/drain regions. Each pulse from the laser can respectively irradiate different portions of the source/drain regions, and a spot area of the laser is less than 50 millimeter2.

Abstract translation: 一种制造半导体器件的方法包括在衬底上形成栅电极，将掺杂剂注入到衬底中并使用激光热退火激活掺杂剂。 在退火期间，激光器和衬底相对于彼此移动，并且激光器和衬底相对于彼此的运动在激活源极/漏极区域的一部分之间和在激活源极/漏极区域的另一部分之间不间断， 漏区。 来自激光器的每个脉冲可以分别照射源极/漏极区域的不同部分，并且激光器的斑点面积小于50毫米2。

公开(公告)号：US07298007B1

公开(公告)日：2007-11-20

申请号：US11171399

申请日：2005-07-01

Applicant: Wiley Eugene Hill ,  Bin Yu

Inventor： Wiley Eugene Hill ,  Bin Yu

IPC: H01L29/76

CPC classification number: H01L27/1108 ,  H01L21/845 ,  H01L27/11 ,  H01L27/1211 ,  H01L29/66803 ,  H01L29/785 ,  Y10S257/903 ,  Y10S438/944

Abstract: A memory device includes multiple fins formed adjacent to one another, a source region, a drain region, a gate, a wordline, and a bitline contact. At least one of the multiple fins is doped with a first type of impurities and at least one other one of the fins is doped with a second type of impurities. The source region is formed at one end of each of the fins and the drain region is formed at an opposite end of each of the fins. The gate is formed over two of the multiple fins, the wordline is formed over each of the multiple fins, and a bitline contact is formed adjacent at least one of the multiple fins.

Abstract translation: 存储器件包括彼此相邻形成的多个鳍，源极区，漏极区，栅极，字线和位线接触。 多个翅片中的至少一个被掺杂有第一类型的杂质，并且至少另外一个翅片掺杂有第二类型的杂质。 源区域形成在每个散热片的一端，并且漏极区域形成在每个散热片的相对端。 栅极形成在多个散热片的两个之上，字线形成在多个散热片的每一个上，并且与多个散热片中的至少一个相邻地形成有位线接触。

公开(公告)号：US20070141791A1

公开(公告)日：2007-06-21

申请号：US11677404

申请日：2007-02-21

Applicant: Ming-Ren Lin ,  Bin Yu

Inventor： Ming-Ren Lin ,  Bin Yu

IPC: H01L21/336

CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/78687

Abstract: A semiconductor device includes a substrate and an insulating layer on the substrate. The semiconductor device also includes a fin structure formed on the insulating layer, where the fin structure includes first and second side surfaces, a dielectric layer formed on the first and second side surfaces of the fin structure, a first gate electrode formed adjacent the dielectric layer on the first side surface of the fin structure, a second gate electrode formed adjacent the dielectric layer on the second side surface of the fin structure, and a doped structure formed on an upper surface of the fin structure in the channel region of the semiconductor device.

Abstract translation: 半导体器件包括衬底和衬底上的绝缘层。 半导体器件还包括形成在绝缘层上的翅片结构，其中鳍结构包括第一和第二侧表面，形成在鳍结构的第一和第二侧表面上的电介质层，形成在电介质层附近的第一栅电极 在翅片结构的第一侧表面上形成与鳍结构的第二侧表面上的电介质层相邻的第二栅电极，以及在半导体器件的沟道区中形成在鳍结构的上表面上的掺杂结构 。

公开(公告)号：US07226764B1

公开(公告)日：2007-06-05

申请号：US09709020

申请日：2000-11-08

Applicant: Christoph Benning ,  Sherrie Lea Sanda ,  Bin Yu

Inventor： Christoph Benning ,  Sherrie Lea Sanda ,  Bin Yu

IPC: C12P7/00 ,  C12N9/00 ,  C12N9/10 ,  C12N1/20 ,  C12N15/00 ,  C12Q21/04 ,  C07H21/04 ,  C12Q1/00 ,  C12Q1/68 ,  C12Q1/48

CPC classification number: C12P19/42

Abstract: The present invention is directed to compositions and methods related to the synthesis and modification of uridine-5′-diphospho-sulfoquinovose (UDP-SQ). In particular, the methods of the present invention comprise the utilization of recombinant enzymes from Arabidopsis thaliana, UDP-glucose, and a sulfur donor to synthesize UDP-SQ, and the subsequent modification of UDP-SQ to form compounds including, but not limited to, 6-sulfo-α-D-quinovosyl diaclyglycerol (SQDG) and alkyl sulfoquinovoside. The compositions and methods of the invention provide a more simple, rapid means of synthesizing UDP-SQ, and the subsequent modification of UDP-SQ to compounds including, but not limited to, SQDG.

Abstract translation: 本发明涉及与尿苷-5'-二磷酸 - 磺基奎诺糖（UDP-SQ）的合成和修饰相关的组合物和方法。 特别地，本发明的方法包括利用来自拟南芥，UDP-葡萄糖和硫供体的重组酶合成UDP-SQ，以及后续的UDP-SQ修饰以形成化合物，包括但不限于 ，6-磺基-α-D-喹喔啉基二甘油（SQDG）和烷基磺基喹诺酮。 本发明的组合物和方法提供了一种更简单，快速的方法来合成UDP-SQ，以及随后将UDP-SQ修饰为化合物，包括但不限于SQDG。

公开(公告)号：US07091068B1

公开(公告)日：2006-08-15

申请号：US10310776

申请日：2002-12-06

Applicant: Shibly S. Ahmed ,  Cyrus E. Tabery ,  Bin Yu

Inventor： Shibly S. Ahmed ,  Cyrus E. Tabery ,  Bin Yu

IPC: H01L21/00

CPC classification number: H01L29/785 ,  H01L29/66795

Abstract: A method of manufacturing a semiconductor device may include forming a fin structure on an insulator and depositing a gate material over the fin structure. The method may also include forming a sacrificial material over the gate material and planarizing the sacrificial material. An antireflective coating may be deposited on the planarized sacrificial material. A gate structure may then be formed by etching the gate material.

Abstract translation: 制造半导体器件的方法可以包括在绝缘体上形成翅片结构，并在栅极结构上沉积栅极材料。 该方法还可以包括在栅极材料上形成牺牲材料并平坦化牺牲材料。 可以在平坦化的牺牲材料上沉积抗反射涂层。 然后可以通过蚀刻栅极材料形成栅极结构。

公开(公告)号：US07064022B1

公开(公告)日：2006-06-20

申请号：US10728844

申请日：2003-12-08

Applicant: Wiley Eugene Hill ,  Ming-Ren Lin ,  Bin Yu

Inventor： Wiley Eugene Hill ,  Ming-Ren Lin ,  Bin Yu

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/336 ,  H01L21/3205 ,  H01L21/4763

CPC classification number: H01L29/7854 ,  H01L21/26586 ,  H01L21/845 ,  H01L27/11 ,  H01L27/1203 ,  H01L29/66795

Abstract: A method forms a semiconductor device from a device that includes a first source region, a first drain region, and a first fin structure that are separated from a second source region, a second drain region, and a second fin structure by an insulating layer. The method may include forming a dielectric layer over the device and removing portions of the dielectric layer to create covered portions and bare portions. The method may also include depositing a gate material over the covered portions and bare portions, doping the first fin structure, the first source region, and the first drain region with a first material, and doping the second fin structure, the second source region, and the second drain region with a second material. The method may further include removing a portion of the gate material over at least one covered portion to form the semiconductor device.

Abstract translation: 一种方法从包括通过绝缘层与第二源极区域，第二漏极区域和第二鳍状结构分离的第一源极区域，第一漏极区域和第一鳍状物结构的器件形成半导体器件。 该方法可以包括在器件上形成电介质层并去除介电层的部分以产生被覆盖部分和裸露部分。 该方法还可以包括在覆盖部分和裸露部分上沉积栅极材料，用第一材料掺杂第一鳍片结构，第一源极区域和第一漏极区域，并掺杂第二鳍片结构，第二源极区域， 和具有第二材料的第二漏区。 该方法还可以包括在至少一个被覆部分上去除栅极材料的一部分以形成半导体器件。

公开(公告)号：US07029959B1

公开(公告)日：2006-04-18

申请号：US10429737

申请日：2003-05-06

Applicant: Chih-Yuh Yang ,  Shibly S. Ahmed ,  Srikanteswara Dakshina-Murhty ,  Cyrus E. Tabery ,  Bin Yu

Inventor： Chih-Yuh Yang ,  Shibly S. Ahmed ,  Srikanteswara Dakshina-Murhty ,  Cyrus E. Tabery ,  Bin Yu

IPC: H01L21/84 ,  H01L21/00

CPC classification number: H01L29/785 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method of manufacturing a semiconductor device may include forming a fin structure on an insulator and depositing a gate material over the fin structure. The method may also include depositing an organic anti-reflective coating on the gate material and forming a gate mask on the organic anti-reflective coating. The organic anti-reflective coating around the gate mask may be removed, and the gate material around the gate mask may be removed to define a gate.

Abstract translation: 制造半导体器件的方法可以包括在绝缘体上形成翅片结构，并在栅极结构上沉积栅极材料。 该方法还可以包括在栅极材料上沉积有机抗反射涂层并在有机抗反射涂层上形成栅极掩模。 可以去除栅极掩模周围的有机抗反射涂层，并且可以去除栅极掩模周围的栅极材料以限定栅极。

公开(公告)号：US06979635B1

公开(公告)日：2005-12-27

申请号：US10759171

申请日：2004-01-20

Applicant: Akif Sultan ,  Qi Xiang ,  Bin Yu

Inventor： Akif Sultan ,  Qi Xiang ,  Bin Yu

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L29/6653 ,  H01L21/28035 ,  H01L21/28123 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S438/976

Abstract: Ultra narrow and thin polycrystalline silicon gate electrodes are formed by patterning a polysilicon gate precursor, reducing its width and height by selectively oxidizing its upper and side surfaces, and then removing the oxidized surfaces. Embodiments include patterning the polysilicon gate precursor with an oxide layer thereunder, ion implanting to form deep source/drain regions, forming a nitride layer on the substrate surface on each side of the polysilicon gate precursor, thermally oxidizing the upper and side surfaces of the polysilicon gate precursor thereby consuming silicon, and then removing the oxidized upper and side surfaces leaving a polysilicon gate electrode with a reduced width and a reduced height. Subsequent processing includes forming shallow source/drain extensions, forming dielectric sidewall spacers on the polysilicon gate electrode and then forming metal silicide layers on the upper surface of the polysilicon gate electrode and over the source/drain regions.

Abstract translation: 通过图案化多晶硅栅极前体，通过选择性地氧化其上表面和侧表面，然后去除氧化表面而减小其宽度和高度来形成超窄和多晶硅栅电极。 实施例包括用其下面的氧化物层图案化多晶硅栅极前体，离子注入以形成深源极/漏极区域，在多晶硅栅极前体的每一侧的衬底表面上形成氮化物层，热氧化多晶硅的上表面和侧表面 从而消耗硅，然后去除氧化的上表面和侧表面，留下具有减小的宽度和降低的高度的多晶硅栅电极。 随后的处理包括形成浅源极/漏极延伸部分，在多晶硅栅电极上形成电介质侧壁间隔物，然后在多晶硅栅极电极的上表面上以及在源极/漏极区域上形成金属硅化物层。

公开(公告)号：US06853020B1

公开(公告)日：2005-02-08

申请号：US10290330

申请日：2002-11-08

Applicant: Bin Yu ,  Judy Xilin An

Inventor： Bin Yu ,  Judy Xilin An

IPC: H01L21/265 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L29/80

CPC classification number: H01L29/785 ,  H01L21/26586 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/7856 ,  H01L29/78684 ,  Y10S257/90

Abstract: A double-gate semiconductor device includes a substrate, an insulating layer, a fin and two gates. The insulating layer is formed on the substrate and the fin is formed on the insulating layer. A first gate is formed on the insulating layer and is located on one side of the fin. A portion of the first gate includes conductive material doped with an n-type dopant. The second gate is formed on the insulating layer and is located on the opposite side of the fin as the first gate. A portion of the second gate includes conductive material doped with a p-type dopant.

Abstract translation: 双栅半导体器件包括衬底，绝缘层，鳍和两个栅极。 绝缘层形成在基板上，并且鳍形成在绝缘层上。 第一栅极形成在绝缘层上并且位于鳍的一侧。 第一栅极的一部分包括掺杂有n型掺杂剂的导电材料。 第二栅极形成在绝缘层上，并且位于作为第一栅极的鳍片的相对侧上。 第二栅极的一部分包括掺杂有p型掺杂剂的导电材料。

公开(公告)号：US06835618B1

公开(公告)日：2004-12-28

申请号：US10633499

申请日：2003-08-05

Applicant: Srikanteswara Dakshina-Murthy ,  Chih-Yuh Yang ,  Bin Yu

Inventor： Srikanteswara Dakshina-Murthy ,  Chih-Yuh Yang ,  Bin Yu

IPC: H01L218242

CPC classification number: H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/78687

Abstract: A method of forming a fin for a fin field effect transistor (FinFET) includes defining a trench in a layer of first material, where a width of an opening of the trench is substantially smaller than a thickness of the layer. The method further includes growing a second material in the trench to form the fin and removing the layer of first material.

Abstract translation: 形成鳍状场效应晶体管（FinFET）的鳍片的方法包括在第一材料层中限定沟槽，其中沟槽的开口的宽度基本上小于该层的厚度。 该方法还包括在沟槽中生长第二材料以形成翅片并去除第一材料层。