公开(公告)号：US5668703A

公开(公告)日：1997-09-16

申请号：US346139

申请日：1994-11-29

Applicant: Domenico Rossi ,  Kazuyuki Tanaka

Inventor： Domenico Rossi ,  Kazuyuki Tanaka

IPC: H02M3/155 ,  H02M3/158 ,  H02M3/335

CPC classification number: H02M3/158

Abstract: A DC--DC boost converter for directly driving a capacitive load employs four switches for cyclically commuting the connection configuration of an energy storing inductor. First and second switches are driven at a relatively high frequency and provide an impulsive charge path of the inductor by connecting one or the other end to a power supply rail. Third and fourth switches are driven in phase opposition to each other at a relatively low frequency and provide a discharge path from one and the other end of the inductor, respectively, toward an output node of the circuit to which the capacitive load is connected.

Abstract translation: 用于直接驱动容性负载的DC-DC升压转换器采用四个开关，用于循环地通过储能电感器的连接配置。 第一和第二开关以相对高的频率驱动，并通过将一端或另一端连接到电源轨提供电感器的脉冲电荷路径。 第三和第四开关以相对较低的频率相互相对地驱动，并且提供从电感器的一端和另一端分别连接到电容负载的电路的输出节点的放电路径。

公开(公告)号：US5663921A

公开(公告)日：1997-09-02

申请号：US391159

申请日：1995-02-21

Applicant: Luigi Pascucci ,  Marco Olivo ,  Carla Maris Golla

Inventor： Luigi Pascucci ,  Marco Olivo ,  Carla Maris Golla

IPC: G11C17/00 ,  G11C7/00 ,  G11C7/22 ,  G11C16/02 ,  G11C16/32

CPC classification number: G11C7/22 ,  G11C16/32

Abstract: A circuit generates flexible timing permitting a slow or fast overall timing configuration, and two configurations of the precharge and detecting intervals by providing both with two (short or long) duration levels. For this purpose, the circuit includes a variable, asymmetrical propagation line composed of a succession of elementary delay elements enabled or disabled on the basis of memorized logic signals, the state of which is determined when debugging the memory in which the circuit is implemented.

Abstract translation: 电路产生灵活的时序，允许缓慢或快速的总体定时配置，以及通过提供两个（短或长）持续时间级别的预充电和检测间隔的两种配置。 为此，该电路包括一个可变的不对称传播线，该可变不对称传播线由基于存储的逻辑信号启用或禁用的一系列基本延迟元件组成，其状态在调试其中实施电路的存储器时被确定。

公开(公告)号：US5663080A

公开(公告)日：1997-09-02

申请号：US524080

申请日：1995-09-06

Applicant: Manlio Sergio Cereda ,  Giancarlo Ginami ,  Enrico Laurin ,  Andrea Ravaglia

Inventor： Manlio Sergio Cereda ,  Giancarlo Ginami ,  Enrico Laurin ,  Andrea Ravaglia

IPC: H01L21/76 ,  H01L21/316 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/8247 ,  H01L21/265

CPC classification number: H01L27/11526 ,  H01L21/76216 ,  H01L21/76218 ,  H01L21/823878 ,  H01L27/11546

Abstract: A process for producing integrated circuits including the steps of: selectively growing field insulating regions of insulating material extending partly inside a substrate having a given type of conductivity; depositing a polycrystalline silicon layer on the substrate; shaping the polycrystalline silicon layer through a mask; and selectively implanting ions of the same conductivity type as the substrate, using the shaping mask, through the field insulating regions. The implanted ions penetrate the substrate and form channel stopper regions beneath the field insulating regions.

Abstract translation: 一种用于制造集成电路的方法，包括以下步骤：选择性地增加部分地具有给定类型导电性的衬底内的绝缘材料的场绝缘区域; 在衬底上沉积多晶硅层; 通过掩模成形多晶硅层; 并且使用成形掩模通过场绝缘区域选择性地注入与衬底相同的导电类型的离子。 注入的离子穿透衬底并在场绝缘区域下方形成通道阻挡区域。

公开(公告)号：US5659516A

公开(公告)日：1997-08-19

申请号：US368211

申请日：1995-01-03

Applicant: Giulio Casagrande ,  Emilio Camerlenghi

Inventor： Giulio Casagrande ,  Emilio Camerlenghi

IPC: G11C17/00 ,  G11C5/14 ,  G11C16/06 ,  G11C16/30 ,  G11C13/00

CPC classification number: G11C16/30 ,  G11C5/147

Abstract: A voltage regulator for electrically programmable non-volatile semiconductor memory devices of the type comprising a gain stage (3), supplied by a programming voltage (Vpp) and having an input terminal connected to a divider (6) of said programming voltage (Vpp) and an output terminal (U) connected to a programming line (5) of at least one memory cell (2) comprises at least one circuit element (4) capable of adapting the line programming voltage (5) to the length (L) of the memory cell (2). This provides a drain voltage, on the bit line of the memory device, which varies according to the actual length of the memory cell.

Abstract translation: 一种用于电可编程非易失性半导体存储器件的电压调节器，包括由编程电压（Vpp）提供并具有连接到所述编程电压（Vpp）的分压器（6）的输入端的增益级（3） 以及连接到至少一个存储单元（2）的编程线（5）的输出端（U）包括至少一个电路元件（4），其能够将线路编程电压（5）适应于 存储单元（2）。 这提供了存储器件的位线上的漏极电压，其根据存储器单元的实际长度而变化。

公开(公告)号：US5657427A

公开(公告)日：1997-08-12

申请号：US475968

申请日：1995-06-07

Applicant: Gianguido Rizzotto ,  Rinaldo Poluzzi ,  Andrea Pagni

Inventor： Gianguido Rizzotto ,  Rinaldo Poluzzi ,  Andrea Pagni

IPC: G05B13/02 ,  G06F9/44 ,  G06N5/04 ,  G06N7/02 ,  G06N7/04 ,  G06F15/18

CPC classification number: G05B13/0275 ,  G06N7/04 ,  Y10S706/90

Abstract: An architecture for an electronic controller operated using fuzzy logic, including an input section with a plurality of inputs for analog or digital signals, a central control unit provided with memories wherein fuzzy logic membership functions are stored, and a defuzzyfier section has its input section composed of a plurality of fuzzyfiers arranged in parallel and independent of one another, each fuzzyfier including an analog input and a digital input for receiving signals from external sensors, and digital outputs connected to the input of a corresponding read-only memory of the central unit to select the address of a memory word.

Abstract translation: 一种用于使用模糊逻辑操作的电子控制器的架构，包括具有用于模拟或数字信号的多个输入的输入部分，设置有存储模糊逻辑隶属函数的存储器的中央控制单元，以及组合其输入部分的去模糊部分 多个并联排列并且彼此独立的模糊器，每个模糊器包括用于从外部传感器接收信号的模拟输入和数字输入，以及连接到中央单元的对应的只读存储器的输入的数字输出， 选择一个内存字的地址。

公开(公告)号：US5653020A

公开(公告)日：1997-08-05

申请号：US550032

申请日：1995-10-30

Applicant: Luigi Romano' ,  Fulvio Tondelli

Inventor： Luigi Romano' ,  Fulvio Tondelli

IPC: B29C37/00 ,  B29C45/14 ,  B29C70/72 ,  H01L21/56 ,  H01R43/00

CPC classification number: B29C45/14655 ,  B29C37/005 ,  B29C70/72 ,  H01L21/565 ,  B29L2031/3425 ,  H01L2224/48247 ,  H01L2924/3511 ,  Y10T29/49121 ,  Y10T29/49146 ,  Y10T29/49172

Abstract: The invention relates to a method for forming a plastic package for an integrated electronic semiconductor device to be encapsulated within a plastic body, being of the type which comprises the step of molding said plastic body so as to fully enclose a semiconductor element, on which an integrated electronic circuit has been formed and which is placed onto a metal leadframe connected electrically to said integrated electronic circuit and carrying a plurality of terminal leads for external electric connection. To compensate the outward bends uncontrollably undergone by the plastic body due to thermal stresses during the molding step, a mold is used which has a cavity delimited by perimeter walls which define a concave-shaped volume. Preferably, at least one of the large walls, a bottom wall and a top wall, has a curvature inwardly of said mold cavity. The curvature values are predetermined to compensate any outward curvature undergone by corresponding surfaces of said plastic body during the molding step. The plastic package thus obtained exhibits, at the end of the molding step, a body having a diversified thickness which is at a maximum near the edges and at a minimum in the central portion; the difference between these thicknesses is proportional to the amount of the relative deformation undergone by the central regions of the body surfaces with respect to the regions near the edges. The plastic body is within ideal overall dimensions.

Abstract translation: 本发明涉及一种用于形成用于封装在塑料体内的集成电子半导体器件的塑料封装件的方法，其包括将所述塑料体模制成完全包围半导体元件的步骤，其中， 已经形成集成电子电路，并且其被放置在与所述集成电子电路电连接的金属引线框架上，并且承载用于外部电连接的多个端子引线。 为了在模制步骤期间由于热应力不可控制地补偿由塑料体引起的向外弯曲，使用具有限定了凹形体积的周边壁限定的空腔的模具。 优选地，所述大壁，底壁和顶壁中的至少一个具有所述模腔内部的曲率。 预定曲率值以补偿在模制步骤期间由所述塑料体的相应表面经历的任何向外弯曲。 由此获得的塑料包装在模制步骤结束时显示出具有多个厚度的主体，该主体在中心部分处在边缘附近最小并且最小; 这些厚度之间的差异与身体表面的中心区域相对于靠近边缘的区域所经受的相对变形量成正比。 塑料体在理想的整体尺寸之内。

公开(公告)号：US5642029A

公开(公告)日：1997-06-24

申请号：US397688

申请日：1995-03-02

Applicant: Giordano Seragnoli

Inventor： Giordano Seragnoli

IPC: H02J7/10 ,  H02J7/00 ,  H02J7/34 ,  H02J9/06 ,  H02J7/04 ,  H01M10/44

CPC classification number: H02J7/0091 ,  H02J7/0068 ,  H02J9/061

Abstract: An auxiliary power supply line for powering the functional circuits of a portable apparatus during recharging of its internal battery by a constant current battery charger is derived from a node upstream of a sensing resistance of the current delivered to the battery under charge and is provided with isolation means.

Abstract translation: 用于通过恒流电池充电器对其内部电池进行再充电期间对便携式设备的功能电路供电的辅助电源线是从传送到被充电电池的电流的感测电阻上游的节点导出的并且被提供隔离 手段。

公开(公告)号：US5638330A

公开(公告)日：1997-06-10

申请号：US456097

申请日：1995-05-30

Applicant: Pierangelo Confalonieri ,  Germano Nicollini

Inventor： Pierangelo Confalonieri ,  Germano Nicollini

IPC: G06F1/24 ,  G11C7/22 ,  H03K3/356 ,  H03K17/00 ,  H03K17/22 ,  G11C7/00

CPC classification number: G11C7/22 ,  H03K17/223 ,  H03K3/356008 ,  H03K2217/0036

Abstract: An initialization circuit for memory registers, having a signal input being applied a supply voltage which rises linearly from a null value, and an initializing output connected to an input of a memory register and on which a voltage signal, being equal or proportional to the supply voltage, during the initialization step, and a null voltage signal, upon the supply voltage dropping below a predetermined tripping value, are produced. Additionally, the circuit has, between the input and the output, a first circuit portion connected to the input; a second circuit portion connected after the first and having a first output connected to the initializing output; and a third, inverting circuit portion having an input connected to a second output of the second portion and an output connected to the first portion to hold off that first portion while the supply voltage drops below the threshold voltage.

Abstract translation: 一种用于存储器寄存器的初始化电路，其具有施加从零值线性上升的电源电压的信号输入和连接到存储器寄存器的输入的初始化输出，并且其上的电压信号等于或成比例 在初始化步骤期间产生电压，并且在电源电压下降到预定跳闸值之前产生零电压信号。 此外，电路在输入和输出之间具有连接到输入端的第一电路部分; 第二电路部分，其在第一电路之后连接并具有连接到初始化输出的第一输出; 以及第三反相电路部分，其具有连接到第二部分的第二输出的输入端和连接到第一部分的输出，以在电源电压降到阈值电压以下时保持该第一部分。

公开(公告)号：US5635822A

公开(公告)日：1997-06-03

申请号：US454648

申请日：1995-05-31

Applicant: Fabio Marchio ,  Alessio Pennisi

Inventor： Fabio Marchio ,  Alessio Pennisi

IPC: H01L27/04 ,  G01R31/28 ,  G05F1/56 ,  H01L21/822 ,  H01L23/58 ,  H01L27/02

CPC classification number: H01L24/49 ,  G01R31/2853 ,  H01L2223/6611 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/01082 ,  H01L2924/01088 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/30105

Abstract: The functioning of a simple voltage regulator loop of an integrated power stage employing a plurality of bond-wires is ensured by realizing a conductive path connecting said pads to each other having a resistance lower by at least two orders of magnitude than the resistance of a voltage sensing divider of the regulation loop. Eventual ruptures of any of the bond-wires remain detectable through a final testing of the integrated circuit.

Abstract translation: 通过实现将所述焊盘彼此连接的导电路径确保具有比电压的电阻低至少两个数量级的电阻来实现采用多个接合线的集成功率级的简单稳压器回路的功能 感应分路器的调节回路。 通过集成电路的最终测试，任何接合线的最终断裂仍然可以检测到。

公开(公告)号：US5627403A

公开(公告)日：1997-05-06

申请号：US473552

申请日：1995-06-06

Applicant: Maurizio Bacchetta ,  Laura Bacci ,  Luca Zanotti

Inventor： Maurizio Bacchetta ,  Laura Bacci ,  Luca Zanotti

IPC: H01L29/78 ,  H01L21/31 ,  H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L23/31 ,  H01L23/532 ,  H01L21/471 ,  H01L23/485

CPC classification number: H01L21/02129 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/3144 ,  H01L21/31608 ,  H01L21/31612 ,  H01L21/31625 ,  H01L21/3185 ,  H01L23/3171 ,  H01L23/5329 ,  H01L2924/0002 ,  Y10S438/902 ,  Y10S438/958

Abstract: A method for improved adhesion between dielectric material layers at their interface during the manufacture of a semiconductor device, comprising operations for forming a first layer (1) of a dielectric material, specifically silicon oxynitride or silicon nitride, on a circuit structure (7) defined on a substrate of a semiconductor material (6) and subsequently forming a second layer (3) of dielectric material (silicon oxynitride or silicon nitride particularly) overlying the first layer (1). Between the first dielectric material layer and the second, a thin oxide layer (2), silicon dioxide in the preferred embodiment, is formed in contact therewith. This interposed oxide (2) serves an adhesion layer function between two superimposed layers (1,3).

Abstract translation: 一种用于在制造半导体器件期间在其界面处改善介电材料层之间的粘合力的方法，包括在电路结构（7）上形成电介质材料（特别是氮氧化硅或氮化硅）的第一层（1）的操作，所述电路结构 在半导体材料（6）的衬底上，随后形成覆盖在第一层（1）上的电介质材料（特别是氮氧化硅或氮化硅）的第二层（3）。 在第一介电材料层和第二介电材料层之间，形成薄的氧化物层（2），优选实施方案中的二氧化硅与其接触。 该插入的氧化物（2）用于两个叠加层（1,3）之间的粘合层功能。