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公开(公告)号:US10692548B2
公开(公告)日:2020-06-23
申请号:US16551593
申请日:2019-08-26
Applicant: Silicon Storage Technology, Inc.
Inventor: Hieu Van Tran , Xian Liu , Nhan Do
IPC: G11C16/06 , G11C7/10 , G11C8/12 , H01L27/11521 , H01L21/28 , G11C16/08 , G11C29/02 , H01L29/423 , H01L29/66 , H01L29/788 , G11C8/08 , G11C8/10 , G11C16/04 , G11C29/12 , H01L27/11524
Abstract: A system and method are disclosed for performing address fault detection in a flash memory system. In one embodiment, a flash memory system comprises a memory array comprising flash memory cells arranged in rows and columns, a row decoder for receiving a row address as an input, the row decoder coupled to a plurality of word lines, wherein each word line is coupled to a row of flash memory cells in the memory array, an address fault detection array comprising a column of memory cells, wherein each of the plurality of word lines is coupled to a memory cell in the column, and an analog comparator for comparing a current drawn by the column with a reference current and for indicating a fault if the current drawn by the column exceeds the reference current.
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422.
公开(公告)号:US20200176460A1
公开(公告)日:2020-06-04
申请号:US16208297
申请日:2018-12-03
Applicant: Silicon Storage Technology, Inc.
Inventor: CATHERINE DECOBERT , HIEU VAN TRAN , NHAN DO
IPC: H01L27/11521 , G11C16/26 , G11C16/16 , H01L29/423 , H01L29/08 , H01L29/10
Abstract: A memory device that includes source and drain regions formed in a semiconductor substrate, with a first channel region of the substrate extending there between. A floating gate is disposed over and insulated from the channel region, wherein the conductivity of the channel region is solely controlled by the floating gate. A control gate is disposed over and insulated from the floating gate. An erase gate is disposed over and insulated from the source region, wherein the erase gate includes a notch that faces and is insulated from an edge of the floating gate. Logic devices are formed on the same substrate. Each logic device has source and drain regions with a channel region extending there between, and a logic gate disposed over and controlling the logic device's channel region.
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423.
公开(公告)号:US20200176459A1
公开(公告)日:2020-06-04
申请号:US16208150
申请日:2018-12-03
Applicant: Silicon Storage Technology, Inc.
Inventor: Feng Zhou , JINHO KIM , XIAN LIU , SERGUEI JOURBA , CATHERINE DECOBERT , NHAN DO
IPC: H01L27/11521 , H01L27/11526 , H01L27/11531 , H01L29/10 , H01L29/423 , H01L29/78 , H01L29/788 , H01L21/28 , H01L29/66
Abstract: A memory device having plurality of upwardly extending semiconductor substrate fins, a memory cell formed on a first fin and a logic device formed on a second fin. The memory cell includes source and drain regions in the first fin with a channel region therebetween, a polysilicon floating gate extending along a first portion of the channel region including the side and top surfaces of the first fin, a metal select gate extending along a second portion of the channel region including the side and top surfaces of the first fin, a polysilicon control gate extending along the floating gate, and a polysilicon erase gate extending along the source region. The logic device includes source and drain regions in the second fin with a second channel region therebetween, and a metal logic gate extending along the second channel region including the side and top surfaces of the second fin.
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公开(公告)号:US10658027B2
公开(公告)日:2020-05-19
申请号:US15002302
申请日:2016-01-20
Applicant: Silicon Storage Technology, Inc.
Inventor: Nhan Do , Xian Liu , Vipin Tiwari , Hieu Van Tran
IPC: H01L29/76 , G11C11/419 , G11C16/04 , G11C16/14 , H01L21/28 , H01L29/423 , H01L29/66 , H01L29/788 , H01L27/11521
Abstract: A method of forming a memory device that includes forming on a substrate, a first insulation layer, a first conductive layer, a second insulation layer, a second conductive layer, a third insulation layer. First trenches are formed through third insulation layer, the second conductive layer, the second insulation layer and the first conductive layer, leaving side portions of the first conductive layer exposed. A fourth insulation layer is formed at the bottom of the first trenches that extends along the exposed portions of the first conductive layer. The first trenches are filled with conductive material. Second trenches are formed through the third insulation layer, the second conductive layer, the second insulation layer and the first conductive layer. Drain regions are formed in the substrate under the second trenches. A pair of memory cells results, with a single continuous channel region extending between drain regions for the pair of memory cells.
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公开(公告)号:US20200065660A1
公开(公告)日:2020-02-27
申请号:US16182237
申请日:2018-11-06
Applicant: Silicon Storage Technology, Inc.
Inventor: Hieu Van Tran , Vipin Tiwari , Mark Reiten , Nhan Do
Abstract: Numerous embodiments are disclosed for a configurable hardware system for use in an analog neural memory system for a deep learning neural network. The components within the configurable hardware system that are configurable can include vector-by-matrix multiplication arrays, summer circuits, activation circuits, inputs, reference devices, neurons, and testing circuits. These devices can be configured to provide various layers or vector-by-matrix multiplication arrays of various sizes, such that the same hardware can be used in analog neural memory systems with different requirements.
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公开(公告)号:US20200051635A1
公开(公告)日:2020-02-13
申请号:US16550248
申请日:2019-08-25
Applicant: Silicon Storage Technology, Inc.
Inventor: Hieu Van Tran , Thuan Vu , Stanley Hong , Anh Ly , Vipin Tiwari , Nhan Do
IPC: G11C16/04 , H01L27/11521 , H01L29/788 , G06N3/08
Abstract: Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. Different calibration algorithms and systems are also disclosed. Compensation measures are utilized to compensate for changes in voltage or current as the number of cells being programmed changes.
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427.
公开(公告)号:US20200019848A1
公开(公告)日:2020-01-16
申请号:US16150606
申请日:2018-10-03
Applicant: Silicon Storage Technology, Inc.
Inventor: Hieu Van Tran , Vipin Tiwari , Nhan Do
Abstract: Numerous embodiments are disclosed for compensating for differences in the slope of the current-voltage characteristic curve among reference transistors, reference memory cells, and flash memory cells during a read operation in an analog neural memory in a deep learning artificial neural network. The embodiments are able to compensate for slope differences during both sub-threshold and linear operation of reference transistors.
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公开(公告)号:US20200013882A1
公开(公告)日:2020-01-09
申请号:US16576348
申请日:2019-09-19
Applicant: Silicon Storage Technology, Inc.
Inventor: Chunming Wang , Leo Xing , Andy Liu , Melvin Diao , Xian Liu , Nhan Do
IPC: H01L29/66 , H01L21/3213 , H01L27/11521 , H01L27/11536 , H01L27/11531 , H01L29/423 , H01L49/02
Abstract: A method of forming a non-volatile memory cell on a substrate having memory cell and logic circuit regions by forming a pair of conductive floating gates in the memory cell region, forming a first source region in the substrate between the pair of floating gates, forming a polysilicon layer in both regions, forming an oxide layer over the polysilicon layer in the logic circuit region, performing a chemical-mechanical polish of the polysilicon layer in the memory cell area leaving a first block of the polysilicon layer between the floating gates that is separated from remaining portions of the polysilicon layer, and selectively etching portions of the polysilicon layer to result in: second and third blocks of the polysilicon layer disposed in outer regions of the memory cell area, and a fourth block of the polysilicon layer in the logic circuit region.
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429.
公开(公告)号:US20200013788A1
公开(公告)日:2020-01-09
申请号:US16422740
申请日:2019-05-24
Applicant: Silicon Storage Technology, Inc.
Inventor: Serguei Jourba , Catherine Decobert , Feng Zhou , Jinho Kim , Xian Liu , Nhan Do
IPC: H01L27/11524 , H01L29/66 , H01L21/8238 , H01L21/8234 , H01L21/768 , H01L27/088 , H01L21/266 , H01L29/788 , H01L29/78 , H01L29/423
Abstract: A method of forming a memory device including a plurality of upwardly extending fins in a semiconductor substrate upper surface. A memory cell is formed on a first fin, and includes spaced apart source and drain regions in the first fin, with a channel region extending along top and opposing side surfaces of the first fin between the source and drain regions. A floating gate extends along a first portion of the channel region. A select gate extends along a second portion of the channel region. A control gate extends along the floating gate. An erase gate extends along the source region. A second fin has a length that extends in a first direction which is perpendicular to a second direction in which a length of the first fin extends. The source region is formed in the first fin at an intersection of the first and second fins.
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公开(公告)号:US20190385685A1
公开(公告)日:2019-12-19
申请号:US16117987
申请日:2018-08-30
Applicant: Silicon Storage Technology, Inc.
Inventor: XIAOZHOU QIANG , XIAO YAN PI , KAI MAN YUE , LI FANG BIAN
Abstract: An improved low-power sense amplifier for use in a flash memory system is disclosed. The reference bit line and selected bit line are pre-charged during a limited period and with limited power consumed. The pre-charge circuit can be trimmed during a configuration process to further optimize power consumption during the pre-charge operation.
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